diff --git a/CMakeLists.txt b/CMakeLists.txt index e499b5e..f0ff06e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -79,6 +79,10 @@ add_library(sim-base STATIC sim/nrfx/hal/nrfx_gpiote.h # includes hal/nrf_gpio.h sim/nrfx/hal/nrf_rtc.h sim/nrfx/hal/nrf_rtc.cpp + sim/nrfx/mdk/nrf.h + sim/nrfx/mdk/nrf52.h + sim/nrfx/mdk/nrf52.cpp + sim/nrfx/mdk/nrf52_bitfields.h # nrf/components/libraries/timer sim/libraries/gpiote/app_gpiote.h # includes hal/nrf_gpio.h ) @@ -88,6 +92,7 @@ target_include_directories(sim-base PUBLIC "sim") target_include_directories(sim-base PUBLIC "sim/libraries/log") # for nrf_log.h target_include_directories(sim-base PUBLIC "sim/nrfx") # for nrfx_log.h and others target_include_directories(sim-base PUBLIC "sim/nrfx/hal") # for nrfx_log.h +target_include_directories(sim-base PUBLIC "sim/nrfx/mdk") # for nrf52_bitfields.h target_include_directories(sim-base PUBLIC "${CMAKE_CURRENT_SOURCE_DIR}") # lv_drv_conf.h target_include_directories(sim-base PUBLIC "${InfiniTime_DIR}/src/libs") @@ -129,8 +134,6 @@ target_sources(infinisim PUBLIC sim/components/heartrate/HeartRateController.cpp sim/components/motion/MotionController.h sim/components/motion/MotionController.cpp - sim/drivers/Watchdog.h - sim/drivers/Watchdog.cpp sim/drivers/Bma421.h sim/drivers/Bma421.cpp sim/drivers/Cst816s.h @@ -201,6 +204,8 @@ target_sources(infinisim PUBLIC ${InfiniTime_DIR}/src/drivers/Spi.cpp ${InfiniTime_DIR}/src/drivers/St7789.h ${InfiniTime_DIR}/src/drivers/St7789.cpp + ${InfiniTime_DIR}/src/drivers/Watchdog.h + ${InfiniTime_DIR}/src/drivers/Watchdog.cpp ${InfiniTime_DIR}/src/touchhandler/TouchHandler.h ${InfiniTime_DIR}/src/touchhandler/TouchHandler.cpp ${InfiniTime_DIR}/src/systemtask/SystemTask.h diff --git a/main.cpp b/main.cpp index 16cfc3f..65ee5c0 100644 --- a/main.cpp +++ b/main.cpp @@ -52,6 +52,7 @@ #include #include +#include // initialize NRF_WDT and NRF_POWER #include #include @@ -420,6 +421,9 @@ public: SDL_RenderPresent(renderer); // Reflects the changes done in the // window. } + init_NRF_WDT(); + init_NRF_POWER(); + motorController.Init(); settingsController.Init(); diff --git a/sim/drivers/Watchdog.cpp b/sim/drivers/Watchdog.cpp deleted file mode 100644 index a550c09..0000000 --- a/sim/drivers/Watchdog.cpp +++ /dev/null @@ -1,153 +0,0 @@ -#include "drivers/Watchdog.h" -//#include -using namespace Pinetime::Drivers; - -namespace { - /// The watchdog is always driven by a 32768kHz clock - constexpr uint32_t ClockFrequency = 32768; - /// Write this value in the reload register to reload the watchdog - constexpr uint32_t ReloadValue = 0x6E524635UL; - - /// Configures the behaviours (pause or run) of the watchdog while the CPU is sleeping or halted by the debugger - /// - /// @param sleepBehaviour Configure the watchdog to either be paused, or kept running, while the CPU is sleeping - /// @param haltBehaviour Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger - void SetBehaviours(Watchdog::SleepBehaviour sleepBehaviour, Watchdog::HaltBehaviour haltBehaviour) { - // NRF_WDT->CONFIG : only the 1st and 4th bits are relevant. - // Bit 0 : Behavior when the CPU is sleeping - // Bit 3 : Behavior when the CPU is halted by the debugger - // O means that the CPU is paused during sleep/halt, 1 means that the watchdog is kept running -// NRF_WDT->CONFIG = static_cast(sleepBehaviour) | static_cast(haltBehaviour); - } - - /// Configure the timeout delay of the watchdog (called CRV, Counter Reload Value, in the documentation). - /// - /// @param timeoutSeconds Timeout of the watchdog, expressed in seconds - void SetTimeout(uint8_t timeoutSeconds) { - // According to the documentation: - // Clock = 32768 - // timeout [s] = ( CRV + 1 ) / Clock - // -> CRV = (timeout [s] * Clock) -1 -// NRF_WDT->CRV = (timeoutSeconds * ClockFrequency) - 1; - } - - /// Enables the first reload register - /// - /// The hardware provides 8 reload registers. To reload the watchdog, all enabled - /// register must be refreshed. - /// - /// This driver only enables the first reload register. - void EnableFirstReloadRegister() { - // RRED (Reload Register Enable) is a bitfield of 8 bits. Each bit represent - // one of the eight reload registers available. - // In this case, we enable only the first one. -// NRF_WDT->RREN |= 1; - } - - /// Returns the reset reason provided by the POWER subsystem - Watchdog::ResetReason GetResetReason() { - /* NRF_POWER->RESETREAS - * -------------------------------------------------------------------------------------------------------------------- * - * Bit | Reason (if bit is set to 1) - * ----|---------------------------------------------------------------------------------------------------------------- * - * 0 | Reset from the pin reset - * 1 | Reset from the watchdog - * 2 | Reset from soft reset - * 3 | Reset from CPU lock-up - * 16 | Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO - * 17 | Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP - * 18 | Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode - * 19 | Reset due to wake up from System OFF mode by NFC field detect - * -------------------------------------------------------------------------------------------------------------------- */ -// const uint32_t reason = NRF_POWER->RESETREAS; -// NRF_POWER->RESETREAS = 0xffffffff; - // sim: always return ResetPin - const uint32_t reason = 0x01; - - uint32_t value = reason & 0x01; // avoid implicit conversion to bool using this temporary variable. - if (value != 0) { - return Watchdog::ResetReason::ResetPin; - } - - value = (reason >> 1u) & 0x01u; - if (value != 0) { - return Watchdog::ResetReason::Watchdog; - } - - value = (reason >> 2u) & 0x01u; - if (value != 0) { - return Watchdog::ResetReason::SoftReset; - } - - value = (reason >> 3u) & 0x01u; - if (value != 0) { - return Watchdog::ResetReason::CpuLockup; - } - - value = (reason >> 16u) & 0x01u; - if (value != 0) { - return Watchdog::ResetReason::SystemOff; - } - - value = (reason >> 17u) & 0x01u; - if (value != 0) { - return Watchdog::ResetReason::LpComp; - } - - value = (reason >> 18u) & 0x01u; - if (value != 0) { - return Watchdog::ResetReason::DebugInterface; - } - - value = (reason >> 19u) & 0x01u; - if (value != 0) { - return Watchdog::ResetReason::NFC; - } - - return Watchdog::ResetReason::HardReset; - } -} - -void Watchdog::Setup(uint8_t timeoutSeconds, SleepBehaviour sleepBehaviour, HaltBehaviour haltBehaviour) { - SetBehaviours(sleepBehaviour, haltBehaviour); - SetTimeout(timeoutSeconds); - EnableFirstReloadRegister(); - - resetReason = ::GetResetReason(); -} - -void Watchdog::Start() { - // Write 1 in the START task to start the watchdog -// NRF_WDT->TASKS_START = 1; -} - -void Watchdog::Reload() { - // Write the reload value 0x6E524635UL to the reload register to reload the watchdog. - // NOTE : This driver enables only the 1st reload register. -// NRF_WDT->RR[0] = ReloadValue; -} - -const char* Pinetime::Drivers::ResetReasonToString(Watchdog::ResetReason reason) { - switch (reason) { - case Watchdog::ResetReason::ResetPin: - return "Reset pin"; - case Watchdog::ResetReason::Watchdog: - return "Watchdog"; - case Watchdog::ResetReason::DebugInterface: - return "Debug interface"; - case Watchdog::ResetReason::LpComp: - return "LPCOMP"; - case Watchdog::ResetReason::SystemOff: - return "System OFF"; - case Watchdog::ResetReason::CpuLockup: - return "CPU Lock-up"; - case Watchdog::ResetReason::SoftReset: - return "Soft reset"; - case Watchdog::ResetReason::NFC: - return "NFC"; - case Watchdog::ResetReason::HardReset: - return "Hard reset"; - default: - return "Unknown"; - } -} diff --git a/sim/drivers/Watchdog.h b/sim/drivers/Watchdog.h deleted file mode 100644 index 66c278c..0000000 --- a/sim/drivers/Watchdog.h +++ /dev/null @@ -1,68 +0,0 @@ -#pragma once -#include -//#include - -namespace Pinetime { - namespace Drivers { - /// Low level driver for the watchdog based on the nRF52832 Product Specification V1.1 - /// - /// This driver initializes the timeout and sleep and halt behaviours of the watchdog - /// in the method Watchdog::Setup(). - /// - /// The watchdog can then be started using the method Watchdog::Start(). At this point, the watchdog runs - /// and will reset the MCU if it's not reloaded before the timeout elapses. - /// - /// The watchdog can be reloaded using Watchdog::Kick(). - /// - /// The watchdog also provide the cause of the last reset (reset pin, watchdog, soft reset, hard reset,... See - /// Watchdog::ResetReasons). - class Watchdog { - public: - /// Indicates the reasons of a reset of the MCU - enum class ResetReason { ResetPin, Watchdog, SoftReset, CpuLockup, SystemOff, LpComp, DebugInterface, NFC, HardReset }; - - /// Behaviours of the watchdog when the CPU is sleeping - enum class SleepBehaviour : uint8_t { - /// Pause watchdog while the CPU is sleeping - Pause = 0, // << WDT_CONFIG_SLEEP_Pos, - /// Keep the watchdog running while the CPU is sleeping - Run = 1 // << WDT_CONFIG_SLEEP_Pos - }; - - /// Behaviours of the watchdog when the CPU is halted by the debugger - enum class HaltBehaviour : uint8_t { - /// Pause watchdog while the CPU is halted by the debugger - Pause = 0, // << WDT_CONFIG_HALT_Pos, - /// Keep the watchdog running while the CPU is halted by the debugger - Run = 1 // << WDT_CONFIG_HALT_Pos - }; - - /// Configures the watchdog with a specific timeout, behaviour when sleeping and when halted by the debugger - /// - /// @param sleepBehaviour Configure the watchdog to either be paused, or kept running, while the CPU is sleeping - /// @param haltBehaviour Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger - void Setup(uint8_t timeoutSeconds, SleepBehaviour sleepBehaviour, HaltBehaviour haltBehaviour); - - /// Starts the watchdog. The watchdog will reset the MCU when the timeout period is elapsed unless you call - /// Watchdog::Kick before the end of the period - void Start(); - - /// Reloads the watchdog. - /// - /// Ensure that you call this function regularly with a period shorter - /// than the timeout period to prevent the watchdog from resetting the MCU. - void Reload(); - - /// Returns the reason of the last reset - ResetReason GetResetReason() const { - return resetReason; - } - - private: - ResetReason resetReason; - }; - - /// Converts a reset reason to a human readable string - const char* ResetReasonToString(Watchdog::ResetReason reason); - } -} diff --git a/sim/nrfx/mdk/nrf.h b/sim/nrfx/mdk/nrf.h new file mode 100644 index 0000000..954e00c --- /dev/null +++ b/sim/nrfx/mdk/nrf.h @@ -0,0 +1,56 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +// shortened version containing just the bits needed for the simulator + +#ifndef NRF_H +#define NRF_H + +/* MDK version */ +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 24 +#define MDK_MICRO_VERSION 1 + +#include "nrf52.h" +#include "nrf52_bitfields.h" + +#endif /* NRF_H */ + diff --git a/sim/nrfx/mdk/nrf52.cpp b/sim/nrfx/mdk/nrf52.cpp new file mode 100644 index 0000000..3cb529d --- /dev/null +++ b/sim/nrfx/mdk/nrf52.cpp @@ -0,0 +1,19 @@ +#include "mdk/nrf52.h" + +// pointer variable used by the rest of the code, and its initialization +NRF_WDT_Type *NRF_WDT; +void init_NRF_WDT() +{ + static NRF_WDT_Type NRF_WDT_object; + NRF_WDT = &NRF_WDT_object; +} + +// pointer variable used by the rest of the code, and its initialization +NRF_POWER_Type *NRF_POWER; +void init_NRF_POWER() +{ + static NRF_POWER_Type NRF_POWER_object; + NRF_POWER = &NRF_POWER_object; + // sim: always return ResetPin as reason for reboot + NRF_POWER->RESETREAS = 0x01; +} diff --git a/sim/nrfx/mdk/nrf52.h b/sim/nrfx/mdk/nrf52.h new file mode 100644 index 0000000..565be0e --- /dev/null +++ b/sim/nrfx/mdk/nrf52.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf52.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 08. February 2019 + * @note Generated by SVDConv V3.3.18 on Friday, 08.02.2019 16:48:11 + * from File 'nrf52.svd', + * last modified on Friday, 08.02.2019 15:48:07 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf52 + * @{ + */ + + +#ifndef NRF52_H +#define NRF52_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +// define empty to make original WDT struct work +#define __OM +#define __IM +#define __IOM + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[0]: Reload request 0 */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + +// simulator specific pointer and initialization function +extern NRF_WDT_Type *NRF_WDT; +void init_NRF_WDT(); + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ +// __IM uint32_t RESERVED[30]; +// __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ +// __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ +// __IM uint32_t RESERVED1[34]; +// __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ +// __IM uint32_t RESERVED2[2]; +// __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ +// __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ +// __IM uint32_t RESERVED3[122]; +// __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ +// __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +// __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ +// __IM uint32_t RESERVED5[9]; +// __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ +// __IM uint32_t RESERVED6[53]; +// __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ +// __IM uint32_t RESERVED7[3]; +// __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ +// __IM uint32_t RESERVED8[2]; +// __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ +// __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ +// __IOM uint32_t RAMON; /*!< (@ 0x00000524) Deprecated register - RAM on/off register (this +// register is retained) */ +// __IM uint32_t RESERVED9[11]; +// __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Deprecated register - RAM on/off register (this +// register is retained) */ +// __IM uint32_t RESERVED10[8]; +// __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ +// __IM uint32_t RESERVED11[225]; +// __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2432 (0x980) */ + +// simulator specific pointer and initialization function +extern NRF_POWER_Type *NRF_POWER; +void init_NRF_POWER(); + +#ifdef __cplusplus +} +#endif + +#endif /* NRF52_H */ + + +/** @} */ /* End of group nrf52 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/sim/nrfx/mdk/nrf52_bitfields.h b/sim/nrfx/mdk/nrf52_bitfields.h new file mode 100644 index 0000000..a49f778 --- /dev/null +++ b/sim/nrfx/mdk/nrf52_bitfields.h @@ -0,0 +1,321 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef __NRF52_BITS_H +#define __NRF52_BITS_H + +// sim: trimmed down original for things we might use in simulator + +/*lint ++flb "Enter library region" */ + +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface 0 */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to Enable interrupt for READY event */ +//#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +//#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +//#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +//#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +//#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ +// +///* Register: SPI_INTENCLR */ +///* Description: Disable interrupt */ +// +///* Bit 2 : Write '1' to Disable interrupt for READY event */ +//#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +//#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +//#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +//#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +//#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ +// +///* Register: SPI_ENABLE */ +///* Description: Enable SPI */ +// +///* Bits 3..0 : Enable or disable SPI */ +//#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +//#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +//#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +//#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ +// +///* Register: SPI_PSEL_SCK */ +///* Description: Pin select for SCK */ +// +///* Bits 31..0 : Pin number configuration for SPI SCK signal */ +//#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */ +//#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */ +//#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ +// +///* Register: SPI_PSEL_MOSI */ +///* Description: Pin select for MOSI */ +// +///* Bits 31..0 : Pin number configuration for SPI MOSI signal */ +//#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */ +//#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */ +//#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ +// +///* Register: SPI_PSEL_MISO */ +///* Description: Pin select for MISO */ +// +///* Bits 31..0 : Pin number configuration for SPI MISO signal */ +//#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */ +//#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */ +//#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ +// +///* Register: SPI_RXD */ +///* Description: RXD register */ +// +///* Bits 7..0 : RX data received. Double buffered */ +//#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +//#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ +// +///* Register: SPI_TXD */ +///* Description: TXD register */ +// +///* Bits 7..0 : TX data to send. Double buffered */ +//#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +//#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ +// +///* Register: SPI_FREQUENCY */ +///* Description: SPI frequency */ +// +///* Bits 31..0 : SPI master data rate */ +//#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +//#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +//#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +//#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +//#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +//#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +//#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +//#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +//#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ +// +///* Register: SPI_CONFIG */ +///* Description: Configuration register */ +// +///* Bit 2 : Serial clock (SCK) polarity */ +//#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +//#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +//#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +//#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ +// +///* Bit 1 : Serial clock (SCK) phase */ +//#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +//#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +//#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +//#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ +// +///* Bit 0 : Bit order */ +//#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +//#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +//#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +//#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ +// +// +///* Peripheral: WDT */ +///* Description: Watchdog Timer */ +// +///* Register: WDT_INTENSET */ +///* Description: Enable interrupt */ +// +///* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */ +//#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +//#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +//#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +//#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +//#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ +// +///* Register: WDT_INTENCLR */ +///* Description: Disable interrupt */ +// +///* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */ +//#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +//#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +//#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +//#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +//#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ +// +///* Register: WDT_RUNSTATUS */ +///* Description: Run status */ +// +///* Bit 0 : Indicates whether or not the watchdog is running */ +//#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +//#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +//#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +//#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ +// +///* Register: WDT_REQSTATUS */ +///* Description: Request status */ +// +///* Bit 7 : Request status for RR[7] register */ +//#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +//#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +//#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +//#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ +// +///* Bit 6 : Request status for RR[6] register */ +//#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +//#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +//#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +//#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ +// +///* Bit 5 : Request status for RR[5] register */ +//#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +//#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +//#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +//#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ +// +///* Bit 4 : Request status for RR[4] register */ +//#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +//#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +//#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +//#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ +// +///* Bit 3 : Request status for RR[3] register */ +//#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +//#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +//#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +//#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ +// +///* Bit 2 : Request status for RR[2] register */ +//#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +//#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +//#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +//#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ +// +///* Bit 1 : Request status for RR[1] register */ +//#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +//#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +//#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +//#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ +// +///* Bit 0 : Request status for RR[0] register */ +//#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +//#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +//#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +//#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ +// +///* Register: WDT_CRV */ +///* Description: Counter reload value */ +// +///* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +//#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +//#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ +// +///* Register: WDT_RREN */ +///* Description: Enable register for reload request registers */ +// +///* Bit 7 : Enable or disable RR[7] register */ +//#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +//#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +//#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +//#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ +// +///* Bit 6 : Enable or disable RR[6] register */ +//#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +//#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +//#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +//#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ +// +///* Bit 5 : Enable or disable RR[5] register */ +//#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +//#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +//#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +//#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ +// +///* Bit 4 : Enable or disable RR[4] register */ +//#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +//#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +//#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +//#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ +// +///* Bit 3 : Enable or disable RR[3] register */ +//#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +//#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +//#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +//#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ +// +///* Bit 2 : Enable or disable RR[2] register */ +//#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +//#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +//#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +//#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ +// +///* Bit 1 : Enable or disable RR[1] register */ +//#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +//#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +//#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +//#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ +// +///* Bit 0 : Enable or disable RR[0] register */ +//#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +//#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +//#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +//#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +///* Register: WDT_RR */ +///* Description: Description collection[0]: Reload request 0 */ +// +///* Bits 31..0 : Reload request register */ +//#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +//#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +//#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif