Add support for LCD (ST7789)
parent
66182d15bc
commit
adf405a230
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
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*
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* The information contained herein is confidential property of Nordic
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* Semiconductor ASA.Terms and conditions of usage are described in detail
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* in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
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*
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* Licensees are granted free, non-transferable use of the information. NO
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* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
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* the file.
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*
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*/
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#include "spi_master_fast.h"
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#include <string.h>
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#include "nrf_gpio.h"
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#include "nrf_delay.h"
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static SPI_config_t spi_config_table[2];
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static NRF_SPI_Type *spi_base[2] = {NRF_SPI0, NRF_SPI1};
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static NRF_SPI_Type *SPI;
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uint32_t* spi_master_init(SPI_module_number_t spi_num, SPI_config_t *spi_config)
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{
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if(spi_num > 1)
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{
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return 0;
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}
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memcpy(&spi_config_table[spi_num], spi_config, sizeof(SPI_config_t));
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/* Configure GPIO pins used for pselsck, pselmosi, pselmiso and pselss for SPI0 */
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nrf_gpio_cfg_output(spi_config->pin_SCK);
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nrf_gpio_cfg_output(spi_config->pin_MOSI);
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nrf_gpio_cfg_input(spi_config->pin_MISO, NRF_GPIO_PIN_NOPULL);
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nrf_gpio_cfg_output(spi_config->pin_CSN);
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/* Configure pins, frequency and mode */
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spi_base[spi_num]->PSELSCK = spi_config->pin_SCK;
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spi_base[spi_num]->PSELMOSI = spi_config->pin_MOSI;
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spi_base[spi_num]->PSELMISO = spi_config->pin_MISO;
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nrf_gpio_pin_set(spi_config->pin_CSN); /* disable Set slave select (inactive high) */
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spi_base[spi_num]->FREQUENCY = (uint32_t)spi_config->frequency << 24;
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spi_base[spi_num]->CONFIG = spi_config->config.SPI_cfg;
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spi_base[spi_num]->EVENTS_READY = 0;
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/* Enable */
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spi_base[spi_num]->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
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return (uint32_t *)spi_base[spi_num];
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}
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bool spi_master_tx_rx(SPI_module_number_t spi_num, uint16_t transfer_size, const uint8_t *tx_data, uint8_t *rx_data)
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{
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volatile uint32_t *SPI_DATA_READY;
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uint32_t tmp;
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if(tx_data == 0 || rx_data == 0)
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{
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return false;
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}
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SPI = spi_base[spi_num];
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SPI_DATA_READY = &SPI->EVENTS_READY;
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/* enable slave (slave select active low) */
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nrf_gpio_pin_clear(spi_config_table[spi_num].pin_CSN);
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*SPI_DATA_READY = 0;
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SPI->TXD = (uint32_t)*tx_data++;
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tmp = (uint32_t)*tx_data++;
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while(--transfer_size)
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{
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SPI->TXD = tmp;
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tmp = (uint32_t)*tx_data++;
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/* Wait for the transaction complete or timeout (about 10ms - 20 ms) */
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while (*SPI_DATA_READY == 0);
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/* clear the event to be ready to receive next messages */
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*SPI_DATA_READY = 0;
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*rx_data++ = SPI->RXD;
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}
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/* Wait for the transaction complete or timeout (about 10ms - 20 ms) */
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while (*SPI_DATA_READY == 0);
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*rx_data = SPI->RXD;
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/* disable slave (slave select active low) */
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nrf_gpio_pin_set(spi_config_table[spi_num].pin_CSN);
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return true;
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}
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bool spi_master_tx(SPI_module_number_t spi_num, uint16_t transfer_size, const uint8_t *tx_data)
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{
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volatile uint32_t dummyread;
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if(tx_data == 0)
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{
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return false;
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}
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SPI = spi_base[spi_num];
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/* enable slave (slave select active low) */
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nrf_gpio_pin_clear(spi_config_table[spi_num].pin_CSN);
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SPI->EVENTS_READY = 0;
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SPI->TXD = (uint32_t)*tx_data++;
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while(--transfer_size)
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{
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SPI->TXD = (uint32_t)*tx_data++;
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/* Wait for the transaction complete or timeout (about 10ms - 20 ms) */
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while (SPI->EVENTS_READY == 0);
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/* clear the event to be ready to receive next messages */
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SPI->EVENTS_READY = 0;
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dummyread = SPI->RXD;
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}
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/* Wait for the transaction complete or timeout (about 10ms - 20 ms) */
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while (SPI->EVENTS_READY == 0);
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dummyread = SPI->RXD;
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/* disable slave (slave select active low) */
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nrf_gpio_pin_set(spi_config_table[spi_num].pin_CSN);
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return true;
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}
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bool spi_master_rx(SPI_module_number_t spi_num, uint16_t transfer_size, uint8_t *rx_data)
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{
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if(rx_data == 0)
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{
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return false;
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}
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SPI = spi_base[spi_num];
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/* enable slave (slave select active low) */
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nrf_gpio_pin_clear(spi_config_table[spi_num].pin_CSN);
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SPI->EVENTS_READY = 0;
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SPI->TXD = 0;
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while(--transfer_size)
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{
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SPI->TXD = 0;
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/* Wait for the transaction complete or timeout (about 10ms - 20 ms) */
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while (SPI->EVENTS_READY == 0);
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/* clear the event to be ready to receive next messages */
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SPI->EVENTS_READY = 0;
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*rx_data++ = SPI->RXD;
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}
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/* Wait for the transaction complete or timeout (about 10ms - 20 ms) */
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while (SPI->EVENTS_READY == 0);
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*rx_data = SPI->RXD;
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/* disable slave (slave select active low) */
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nrf_gpio_pin_set(spi_config_table[spi_num].pin_CSN);
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return true;
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}
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@ -0,0 +1,147 @@
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/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
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*
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* The information contained herein is confidential property of Nordic
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* Semiconductor ASA.Terms and conditions of usage are described in detail
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* in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
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*
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* Licensees are granted free, non-transferable use of the information. NO
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* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
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* the file.
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*
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*/
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#ifndef __SPI_MASTER_FAST_H
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#define __SPI_MASTER_FAST_H
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#include <stdbool.h>
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#include <stdint.h>
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#define SPI_FAST_DEFAULT_CONFIG {.pin_SCK = 1, .pin_MOSI = 2, .pin_MISO = 3, .pin_CSN = 4, \
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.frequency = SPI_FREQ_1MBPS, .config.fields.mode = 0, .config.fields.bit_order = SPI_BITORDER_MSB_LSB}
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/**
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* SPI master operating frequency
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*/
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typedef enum
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{
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SPI_FREQ_125KBPS = 0x02, /*!< drive SClk with frequency 125Kbps */
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SPI_FREQ_250KBPS = 0x04, /*!< drive SClk with frequency 250Kbps */
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SPI_FREQ_500KBPS = 0x08, /*!< drive SClk with frequency 500Kbps */
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SPI_FREQ_1MBPS = 0x10, /*!< drive SClk with frequency 1Mbps */
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SPI_FREQ_2MBPS = 0x20, /*!< drive SClk with frequency 2Mbps */
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SPI_FREQ_4MBPS = 0x40, /*!< drive SClk with frequency 4Mbps */
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SPI_FREQ_8MBPS = 0x80 /*!< drive SClk with frequency 8Mbps */
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} SPI_frequency_t;
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/**
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* SPI master module number
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*/
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typedef enum
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{
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SPI0 = 0, /*!< SPI module 0 */
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SPI1 /*!< SPI module 1 */
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} SPI_module_number_t;
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/**
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* SPI mode
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*/
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typedef enum
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{
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//------------------------Clock polarity 0, Clock starts with level 0-------------------------------------------
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SPI_MODE0 = 0, /*!< Sample data at rising edge of clock and shift serial data at falling edge */
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SPI_MODE1, /*!< sample data at falling edge of clock and shift serial data at rising edge */
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//------------------------Clock polarity 1, Clock starts with level 1-------------------------------------------
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SPI_MODE2, /*!< sample data at falling edge of clock and shift serial data at rising edge */
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SPI_MODE3 /*!< Sample data at rising edge of clock and shift serial data at falling edge */
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} SPI_mode_t;
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/**
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* SPI master bit ordering
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*/
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typedef enum
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{
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SPI_BITORDER_MSB_LSB = 0, /*!< Most significant to least significant bit */
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SPI_BITORDER_LSB_MSB /*!< Least significant to most significant bit */
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} SPI_bit_order_t;
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/**
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* Struct containing all parameters necessary to configure the SPI interface
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*/
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typedef struct
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{
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union
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{
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uint8_t SPI_cfg; /*!< Bit mode and bit order merged, as in the SPI CONFIG register */
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struct
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{
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uint8_t bit_order : 1; /*!< SPI master bit order */
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uint8_t mode : 2; /*!< SPI master mode */
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uint8_t : 5; /*!< Padding */
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}fields;
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}config;
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uint8_t frequency; /*!< SPI master frequency */
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uint8_t pin_SCK; /*!< SPI master SCK pin */
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uint8_t pin_MOSI; /*!< SPI master MOSI pin */
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uint8_t pin_MISO; /*!< SPI master MISO pin */
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uint8_t pin_CSN; /*!< SPI master chip select pin */
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} SPI_config_t;
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/**
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* Initializes given SPI master with given configuration.
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*
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* After initializing the given SPI master with given configuration, this function also test if the
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* SPI slave is responding with the configurations by transmitting few test bytes. If the slave did not
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* respond then error is returned and contents of the rx_data are invalid.
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*
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* @param module_number SPI master number (SPIModuleNumber) to initialize.
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* @param pointer to a struct of type @ref SPIConfig_t containing the SPI configuration parameters.
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* @return
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* @retval pointer to direct physical address of the requested SPI module if init was successful
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* @retval 0, if either init failed or slave did not respond to the test transfer
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*/
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uint32_t* spi_master_init(SPI_module_number_t spi_num, SPI_config_t *spi_config);
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/**
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* Transmit/receive data over SPI bus.
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*
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* @note Make sure at least transfer_size number of bytes is allocated in tx_data/rx_data.
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*
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* @param spi_num SPI master number (SPIModuleNumber)
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* @param transfer_size number of bytes to transmit/receive over SPI master
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* @param tx_data pointer to the data that needs to be transmitted
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* @param rx_data pointer to the data that needs to be received
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* @return
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* @retval true if transmit/reveive of transfer_size were completed.
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* @retval false if transmit/reveive of transfer_size were not complete and tx_data/rx_data points to invalid data.
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*/
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bool spi_master_tx_rx(SPI_module_number_t spi_num, uint16_t transfer_size, const uint8_t *tx_data, uint8_t *rx_data);
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/**
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* Transmit data over SPI bus.
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*
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* @note Make sure at least transfer_size number of bytes is allocated in tx_data.
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*
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* @param spi_num SPI master number (SPIModuleNumber)
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* @param transfer_size number of bytes to transmit/receive over SPI master
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* @param tx_data pointer to the data that needs to be transmitted
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* @return
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* @retval true if transmit/reveive of transfer_size were completed.
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* @retval false if transmit/reveive of transfer_size were not complete and tx_data/rx_data points to invalid data.
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*/
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bool spi_master_tx(SPI_module_number_t spi_num, uint16_t transfer_size, const uint8_t *tx_data);
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/**
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* Receive data over SPI bus.
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*
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* @note Make sure at least transfer_size number of bytes is allocated in rx_data.
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*
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* @param spi_num SPI master number (SPIModuleNumber)
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* @param transfer_size number of bytes to transmit/receive over SPI master
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* @param rx_data pointer to the data that needs to be received
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* @return
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* @retval true if transmit/reveive of transfer_size were completed.
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* @retval false if transmit/reveive of transfer_size were not complete and tx_data/rx_data points to invalid data.
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*/
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bool spi_master_rx(SPI_module_number_t spi_num, uint16_t transfer_size, uint8_t *rx_data);
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#endif
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//
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// Created by jf on 12/2/19.
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//
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#include <hal/nrf_gpio.h>
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#include <libraries/delay/nrf_delay.h>
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#include "st7789.h"
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#include "spi_master_fast.h"
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using namespace Pinetime::Drivers;
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ret_code_t st7789::Init() {
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InitHw();
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InitCommands();
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}
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ret_code_t st7789::InitHw() const {
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nrf_gpio_cfg_output(ST7735_DC_PIN);
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SPI_config_t spi_config;
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spi_config.pin_SCK = ST7735_SCK_PIN;
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spi_config.pin_MOSI = ST7735_MOSI_PIN;
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spi_config.pin_MISO = ST7735_MISO_PIN;
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spi_config.pin_CSN = ST7735_SS_PIN;
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spi_config.frequency = SPI_FREQ_8MBPS;
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spi_config.config.fields.mode = SPI_MODE3;
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spi_config.config.fields.bit_order = SPI_BITORDER_MSB_LSB;
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spi_master_init(SPI0, &spi_config);
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return 0;
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}
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void st7789::InitCommands() {
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SoftwareReset();
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SleepOut();
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ColMod();
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MemoryDataAccessControl();
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ColumnAddressSet();
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RowAddressSet();
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DisplayInversionOn();
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NormalModeOn();
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DisplayOn();
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}
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void st7789::WriteCommand(uint8_t cmd) {
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nrf_gpio_pin_clear(ST7735_DC_PIN);
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WriteSpi(&cmd, 1);
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}
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void st7789::WriteData(uint8_t data) {
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nrf_gpio_pin_set(ST7735_DC_PIN);
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WriteSpi(&data, 1);
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}
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void st7789::WriteSpi(const uint8_t* data, size_t size) {
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// APP_ERROR_CHECK(nrf_drv_spi_transfer(&spi, data, size, nullptr, 0));
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spi_master_tx(SPI0, size, data);
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}
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void st7789::SoftwareReset() {
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WriteCommand(static_cast<uint8_t>(Commands::SoftwareReset));
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nrf_delay_ms(150);
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}
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void st7789::SleepOut() {
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WriteCommand(static_cast<uint8_t>(Commands::SleepOut));
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nrf_delay_ms(500);
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}
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void st7789::ColMod() {
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WriteCommand(static_cast<uint8_t>(Commands::ColMod));
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WriteData(0x55);
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nrf_delay_ms(10);
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}
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void st7789::MemoryDataAccessControl() {
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WriteCommand(static_cast<uint8_t>(Commands::MemoryDataAccessControl));
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WriteData(0x00);
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}
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void st7789::ColumnAddressSet() {
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WriteCommand(static_cast<uint8_t>(Commands::ColumnAddressSet));
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WriteData(0x00);
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WriteData(0x00);
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WriteData(Height >> 8);
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WriteData(Height & 0xff);
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}
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void st7789::RowAddressSet() {
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WriteCommand(static_cast<uint8_t>(Commands::RowAddressSet));
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WriteData(0x00);
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WriteData(0x00);
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WriteData(Width >> 8);
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WriteData(Width & 0xff);
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}
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void st7789::DisplayInversionOn() {
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WriteCommand(static_cast<uint8_t>(Commands::DisplayInversionOn));
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nrf_delay_ms(10);
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}
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void st7789::NormalModeOn() {
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WriteCommand(static_cast<uint8_t>(Commands::NormalModeOn));
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nrf_delay_ms(10);
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}
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void st7789::DisplayOn() {
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WriteCommand(static_cast<uint8_t>(Commands::DisplayOn));
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nrf_delay_ms(500);
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}
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void st7789::FillRectangle(uint16_t x, uint16_t y, uint16_t width, uint16_t height, uint16_t color) {
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// rudimentary clipping (drawChar w/big text requires this)
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if((x >= Width) || (y >= Height)) return;
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if((x + width - 1) >= Width) width = Width - x;
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if((y + height - 1) >= Height) height = Height - y;
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SetAddrWindow(0+x, ST7789_ROW_OFFSET+y, x+width-1, y+height-1);
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uint8_t hi = color >> 8, lo = color;
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uint32_t c = color + (color << 16);
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nrf_gpio_pin_set(ST7735_DC_PIN);
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for(y=height+ST7789_ROW_OFFSET; y>ST7789_ROW_OFFSET; y--) {
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for(x=width; x>0; x--) {
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WriteSpi(reinterpret_cast<const uint8_t *>(&c), 4);
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}
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}
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}
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void st7789::SetAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1) {
|
||||
WriteCommand(static_cast<uint8_t>(Commands::ColumnAddressSet));
|
||||
WriteData(x0 >> 8);
|
||||
WriteData(x0 & 0xff);
|
||||
WriteData(x1 >> 8);
|
||||
WriteData(x1 & 0xff);
|
||||
|
||||
WriteCommand(static_cast<uint8_t>(Commands::RowAddressSet));
|
||||
WriteData(y0>>8);
|
||||
WriteData(y0 & 0xff);
|
||||
WriteData(y1 >> 8);
|
||||
WriteData(y1 & 0xff);
|
||||
|
||||
WriteToRam();
|
||||
}
|
||||
|
||||
void st7789::WriteToRam() {
|
||||
WriteCommand(static_cast<uint8_t>(Commands::WriteToRam));
|
||||
}
|
||||
|
||||
void st7789::DisplayOff() {
|
||||
WriteCommand(static_cast<uint8_t>(Commands::DisplayOff));
|
||||
nrf_delay_ms(500);
|
||||
}
|
||||
|
||||
void st7789::Uninit() {
|
||||
|
||||
}
|
||||
|
||||
void st7789::DrawPixel(uint16_t x, uint16_t y, uint32_t color) {
|
||||
if((x < 0) ||(x >= Width) || (y < 0) || (y >= Height)) return;
|
||||
|
||||
SetAddrWindow(x, y, x+1, y+1);
|
||||
|
||||
nrf_gpio_pin_set(ST7735_DC_PIN);
|
||||
WriteSpi(reinterpret_cast<const uint8_t *>(&color), 2);
|
||||
}
|
||||
|
Loading…
Reference in New Issue