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@ -24,9 +24,14 @@ static u32 uniform_write_buffer[4];
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static u32 vs_binary_write_offset = 0;
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static u32 vs_swizzle_write_offset = 0;
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static inline void WritePicaReg(u32 id, u32 value) {
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static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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if (id >= registers.NumIds())
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return;
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// TODO: Figure out how register masking acts on e.g. vs_uniform_setup.set_value
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u32 old_value = registers[id];
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registers[id] = value;
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registers[id] = (old_value & ~mask) | (value & mask);
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switch(id) {
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// It seems like these trigger vertex rendering
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@ -215,14 +220,17 @@ static std::ptrdiff_t ExecuteCommandBlock(const u32* first_command_word) {
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u32* read_pointer = (u32*)first_command_word;
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// TODO: Take parameter mask into consideration!
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const u32 write_mask = ((header.parameter_mask & 0x1) ? (0xFFu << 0) : 0u) |
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((header.parameter_mask & 0x2) ? (0xFFu << 8) : 0u) |
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((header.parameter_mask & 0x4) ? (0xFFu << 16) : 0u) |
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((header.parameter_mask & 0x8) ? (0xFFu << 24) : 0u);
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WritePicaReg(header.cmd_id, *read_pointer);
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WritePicaReg(header.cmd_id, *read_pointer, write_mask);
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read_pointer += 2;
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for (int i = 1; i < 1+header.extra_data_length; ++i) {
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u32 cmd = header.cmd_id + ((header.group_commands) ? i : 0);
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WritePicaReg(cmd, *read_pointer);
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WritePicaReg(cmd, *read_pointer, write_mask);
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++read_pointer;
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}
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