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@ -401,22 +401,47 @@ struct Regs {
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TevStageConfig tev_stage3;
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INSERT_PADDING_WORDS(0x3);
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enum class FogMode : u32 {
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None = 0,
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Fog = 5,
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Gas = 7,
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};
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union {
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// Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in
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// these masks are set
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BitField< 8, 4, u32> update_mask_rgb;
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BitField<12, 4, u32> update_mask_a;
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BitField<0, 3, FogMode> fog_mode;
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BitField<16, 1, u32> fog_flip;
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bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_rgb & (1 << stage_index));
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}
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union {
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// Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in
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// these masks are set
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BitField< 8, 4, u32> update_mask_rgb;
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BitField<12, 4, u32> update_mask_a;
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bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_a & (1 << stage_index));
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}
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} tev_combiner_buffer_input;
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bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_rgb & (1 << stage_index));
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}
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bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_a & (1 << stage_index));
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}
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} tev_combiner_buffer_input;
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};
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union {
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u32 raw;
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BitField< 0, 8, u32> r;
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BitField< 8, 8, u32> g;
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BitField<16, 8, u32> b;
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} fog_color;
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INSERT_PADDING_WORDS(0x4);
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BitField<0, 16, u32> fog_lut_offset;
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INSERT_PADDING_WORDS(0x1);
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u32 fog_lut_data[8];
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INSERT_PADDING_WORDS(0xf);
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TevStageConfig tev_stage4;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage5;
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@ -1318,6 +1343,10 @@ ASSERT_REG_POSITION(tev_stage1, 0xc8);
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ASSERT_REG_POSITION(tev_stage2, 0xd0);
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ASSERT_REG_POSITION(tev_stage3, 0xd8);
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ASSERT_REG_POSITION(tev_combiner_buffer_input, 0xe0);
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ASSERT_REG_POSITION(fog_mode, 0xe0);
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ASSERT_REG_POSITION(fog_color, 0xe1);
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ASSERT_REG_POSITION(fog_lut_offset, 0xe6);
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ASSERT_REG_POSITION(fog_lut_data, 0xe8);
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ASSERT_REG_POSITION(tev_stage4, 0xf0);
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ASSERT_REG_POSITION(tev_stage5, 0xf8);
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ASSERT_REG_POSITION(tev_combiner_buffer_color, 0xfd);
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