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@ -14,6 +14,7 @@
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namespace Tegra {
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constexpr u32 MacroRegistersStart = 0xE00;
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constexpr u32 ComputeInline = 0x6D;
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DmaPusher::DmaPusher(Core::System& system_, GPU& gpu_, MemoryManager& memory_manager_,
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Control::ChannelState& channel_state_)
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@ -83,12 +84,35 @@ bool DmaPusher::Step() {
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dma_state.dma_get, command_list_header.size * sizeof(u32));
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}
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}
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Core::Memory::GpuGuestMemory<Tegra::CommandHeader,
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Core::Memory::GuestMemoryFlags::UnsafeRead>
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headers(memory_manager, dma_state.dma_get, command_list_header.size, &command_headers);
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ProcessCommands(headers);
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const auto safe_process = [&] {
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Core::Memory::GpuGuestMemory<Tegra::CommandHeader,
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Core::Memory::GuestMemoryFlags::SafeRead>
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headers(memory_manager, dma_state.dma_get, command_list_header.size,
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&command_headers);
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ProcessCommands(headers);
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};
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const auto unsafe_process = [&] {
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Core::Memory::GpuGuestMemory<Tegra::CommandHeader,
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Core::Memory::GuestMemoryFlags::UnsafeRead>
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headers(memory_manager, dma_state.dma_get, command_list_header.size,
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&command_headers);
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ProcessCommands(headers);
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};
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if (Settings::IsGPULevelHigh()) {
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if (dma_state.method >= MacroRegistersStart) {
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unsafe_process();
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return true;
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}
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if (subchannel_type[dma_state.subchannel] == Engines::EngineTypes::KeplerCompute &&
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dma_state.method == ComputeInline) {
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unsafe_process();
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return true;
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}
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safe_process();
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return true;
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}
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unsafe_process();
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}
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return true;
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}
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