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@ -16,7 +16,34 @@ u32 ShaderIR::DecodeRegisterSetPredicate(BasicBlock& bb, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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UNIMPLEMENTED();
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UNIMPLEMENTED_IF(instr.r2p.mode != Tegra::Shader::R2pMode::Pr);
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const Node apply_mask = [&]() {
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switch (opcode->get().GetId()) {
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case OpCode::Id::R2P_IMM:
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return Immediate(static_cast<u32>(instr.r2p.immediate_mask));
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default:
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UNREACHABLE();
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return Immediate(static_cast<u32>(instr.r2p.immediate_mask));
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}
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}();
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const Node mask =
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Operation(OperationCode::ULogicalShiftRight, NO_PRECISE, GetRegister(instr.gpr8),
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Immediate(static_cast<u32>(instr.r2p.byte)));
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constexpr u32 programmable_preds = 7;
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for (u64 pred = 0; pred < programmable_preds; ++pred) {
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const Node shift = Immediate(1u << static_cast<u32>(pred));
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const Node apply_compare = Operation(OperationCode::UBitwiseAnd, NO_PRECISE, apply_mask, shift);
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const Node condition = Operation(OperationCode::LogicalUEqual, apply_compare, Immediate(0));
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const Node value_compare = Operation(OperationCode::UBitwiseAnd, NO_PRECISE, mask, shift);
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const Node value = Operation(OperationCode::LogicalUEqual, value_compare, Immediate(0));
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const Node code = Operation(OperationCode::LogicalAssign, GetPredicate(pred), value);
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bb.push_back(Conditional(condition, {code}));
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}
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return pc;
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}
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