@ -83,6 +83,25 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
ASSERT_MSG ( regs . code_address . CodeAddress ( ) = = 0 , " Unexpected CODE_ADDRESS register value. " ) ;
break ;
}
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 0 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 1 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 2 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 3 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 4 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 5 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 6 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 7 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 8 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 9 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 10 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 11 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 12 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 13 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 14 ] ) :
case MAXWELL3D_REG_INDEX ( const_buffer . cb_data [ 15 ] ) : {
ProcessCBData ( value ) ;
break ;
}
case MAXWELL3D_REG_INDEX ( cb_bind [ 0 ] . raw_config ) : {
ProcessCBBind ( Regs : : ShaderStage : : Vertex ) ;
break ;
@ -194,5 +213,22 @@ void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
buffer . size = regs . const_buffer . cb_size ;
}
void Maxwell3D : : ProcessCBData ( u32 value ) {
// Write the input value to the current const buffer at the current position.
GPUVAddr buffer_address = regs . const_buffer . BufferAddress ( ) ;
ASSERT ( buffer_address ! = 0 ) ;
// Don't allow writing past the end of the buffer.
ASSERT ( regs . const_buffer . cb_pos + sizeof ( u32 ) < = regs . const_buffer . cb_size ) ;
VAddr address =
memory_manager . PhysicalToVirtualAddress ( buffer_address + regs . const_buffer . cb_pos ) ;
Memory : : Write32 ( address , value ) ;
// Increment the current buffer position.
regs . const_buffer . cb_pos = regs . const_buffer . cb_pos + 4 ;
}
} // namespace Engines
} // namespace Tegra