shader: Implement HFMA2
FernandoS27
ameerj
parent
76c8a962ac
commit
28dff6a629
@ -0,0 +1,170 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_helper.h"
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namespace Shader::Maxwell {
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namespace {
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void HFMA2(TranslatorVisitor& v, u64 insn, Merge merge, Swizzle swizzle_a, bool neg_b, bool neg_c,
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Swizzle swizzle_b, Swizzle swizzle_c, const IR::U32& src_b, const IR::U32& src_c,
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bool sat, HalfPrecision precision) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_a;
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} const hfma2{insn};
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auto [lhs_a, rhs_a]{Extract(v.ir, v.X(hfma2.src_a), swizzle_a)};
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auto [lhs_b, rhs_b]{Extract(v.ir, src_b, swizzle_b)};
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auto [lhs_c, rhs_c]{Extract(v.ir, src_c, swizzle_c)};
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const bool promotion{lhs_a.Type() != lhs_b.Type() || lhs_a.Type() != lhs_c.Type()};
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if (promotion) {
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if (lhs_a.Type() == IR::Type::F16) {
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lhs_a = v.ir.FPConvert(32, lhs_a);
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rhs_a = v.ir.FPConvert(32, rhs_a);
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}
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if (lhs_b.Type() == IR::Type::F16) {
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lhs_b = v.ir.FPConvert(32, lhs_b);
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rhs_b = v.ir.FPConvert(32, rhs_b);
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}
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if (lhs_c.Type() == IR::Type::F16) {
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lhs_c = v.ir.FPConvert(32, lhs_c);
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rhs_c = v.ir.FPConvert(32, rhs_c);
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}
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}
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lhs_b = v.ir.FPAbsNeg(lhs_b, false, neg_b);
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rhs_b = v.ir.FPAbsNeg(rhs_b, false, neg_b);
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lhs_c = v.ir.FPAbsNeg(lhs_c, false, neg_c);
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rhs_c = v.ir.FPAbsNeg(rhs_c, false, neg_c);
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const IR::FpControl fp_control{
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.no_contraction{true},
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.rounding{IR::FpRounding::DontCare},
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.fmz_mode{HalfPrecision2FmzMode(precision)},
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};
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IR::F16F32F64 lhs{v.ir.FPFma(lhs_a, lhs_b, lhs_c, fp_control)};
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IR::F16F32F64 rhs{v.ir.FPFma(rhs_a, rhs_b, rhs_c, fp_control)};
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if (precision == HalfPrecision::FMZ && !sat) {
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// Do not implement FMZ if SAT is enabled, as it does the logic for us.
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// On D3D9 mode, anything * 0 is zero, even NAN and infinity
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const IR::F32 zero{v.ir.Imm32(0.0f)};
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const IR::U1 lhs_zero_a{v.ir.FPEqual(lhs_a, zero)};
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const IR::U1 lhs_zero_b{v.ir.FPEqual(lhs_b, zero)};
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const IR::U1 lhs_any_zero{v.ir.LogicalOr(lhs_zero_a, lhs_zero_b)};
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lhs = IR::F16F32F64{v.ir.Select(lhs_any_zero, lhs_c, lhs)};
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const IR::U1 rhs_zero_a{v.ir.FPEqual(rhs_a, zero)};
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const IR::U1 rhs_zero_b{v.ir.FPEqual(rhs_b, zero)};
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const IR::U1 rhs_any_zero{v.ir.LogicalOr(rhs_zero_a, rhs_zero_b)};
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rhs = IR::F16F32F64{v.ir.Select(rhs_any_zero, rhs_c, rhs)};
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}
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if (sat) {
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lhs = v.ir.FPSaturate(lhs);
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rhs = v.ir.FPSaturate(rhs);
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}
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if (promotion) {
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lhs = v.ir.FPConvert(16, lhs);
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rhs = v.ir.FPConvert(16, rhs);
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}
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v.X(hfma2.dest_reg, MergeResult(v.ir, hfma2.dest_reg, lhs, rhs, merge));
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}
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void HFMA2(TranslatorVisitor& v, u64 insn, bool neg_b, bool neg_c, Swizzle swizzle_b,
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Swizzle swizzle_c, const IR::U32& src_b, const IR::U32& src_c, bool sat,
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HalfPrecision precision) {
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union {
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u64 raw;
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BitField<47, 2, Swizzle> swizzle_a;
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BitField<49, 2, Merge> merge;
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} const hfma2{insn};
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HFMA2(v, insn, hfma2.merge, hfma2.swizzle_a, neg_b, neg_c, swizzle_b, swizzle_c, src_b, src_c,
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sat, precision);
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}
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} // namespace
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void TranslatorVisitor::HFMA2_reg(u64 insn) {
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union {
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u64 raw;
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BitField<28, 2, Swizzle> swizzle_b;
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BitField<32, 1, u64> saturate;
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BitField<31, 1, u64> neg_b;
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BitField<30, 1, u64> neg_c;
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BitField<35, 2, Swizzle> swizzle_c;
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BitField<37, 2, HalfPrecision> precision;
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} const hfma2{insn};
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HFMA2(*this, insn, hfma2.neg_b != 0, hfma2.neg_c != 0, hfma2.swizzle_b, hfma2.swizzle_c,
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GetReg20(insn), GetReg39(insn), hfma2.saturate != 0, hfma2.precision);
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}
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void TranslatorVisitor::HFMA2_rc(u64 insn) {
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union {
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u64 raw;
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BitField<51, 1, u64> neg_c;
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BitField<52, 1, u64> saturate;
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BitField<53, 2, Swizzle> swizzle_b;
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BitField<56, 1, u64> neg_b;
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BitField<57, 2, HalfPrecision> precision;
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} const hfma2{insn};
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HFMA2(*this, insn, hfma2.neg_b != 0, hfma2.neg_c != 0, hfma2.swizzle_b, Swizzle::F32,
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GetReg39(insn), GetCbuf(insn), hfma2.saturate != 0, hfma2.precision);
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}
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void TranslatorVisitor::HFMA2_cr(u64 insn) {
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union {
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u64 raw;
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BitField<51, 1, u64> neg_c;
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BitField<52, 1, u64> saturate;
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BitField<53, 2, Swizzle> swizzle_c;
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BitField<56, 1, u64> neg_b;
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BitField<57, 2, HalfPrecision> precision;
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} const hfma2{insn};
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HFMA2(*this, insn, hfma2.neg_b != 0, hfma2.neg_c != 0, Swizzle::F32, hfma2.swizzle_c,
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GetCbuf(insn), GetReg39(insn), hfma2.saturate != 0, hfma2.precision);
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}
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void TranslatorVisitor::HFMA2_imm(u64 insn) {
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union {
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u64 raw;
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BitField<51, 1, u64> neg_c;
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BitField<52, 1, u64> saturate;
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BitField<53, 2, Swizzle> swizzle_c;
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BitField<56, 1, u64> neg_high;
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BitField<30, 9, u64> high;
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BitField<29, 1, u64> neg_low;
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BitField<20, 9, u64> low;
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BitField<57, 2, HalfPrecision> precision;
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} const hfma2{insn};
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const u32 imm{static_cast<u32>(hfma2.low << 6) | ((hfma2.neg_low != 0 ? 1 : 0) << 15) |
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static_cast<u32>(hfma2.high << 22) | ((hfma2.neg_high != 0 ? 1 : 0) << 31)};
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HFMA2(*this, insn, false, hfma2.neg_c != 0, Swizzle::H1_H0, hfma2.swizzle_c, ir.Imm32(imm),
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GetReg39(insn), hfma2.saturate != 0, hfma2.precision);
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}
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void TranslatorVisitor::HFMA2_32I(u64 insn) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> src_c;
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BitField<20, 32, u64> imm32;
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BitField<52, 1, u64> neg_c;
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BitField<53, 2, Swizzle> swizzle_a;
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BitField<55, 2, HalfPrecision> precision;
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} const hfma2{insn};
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const u32 imm{static_cast<u32>(hfma2.imm32)};
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HFMA2(*this, insn, Merge::H1_H0, hfma2.swizzle_a, false, hfma2.neg_c != 0, Swizzle::H1_H0,
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Swizzle::H1_H0, ir.Imm32(imm), X(hfma2.src_c), false, hfma2.precision);
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}
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} // namespace Shader::Maxwell
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