|
|
|
@ -6,6 +6,7 @@
|
|
|
|
|
#include <array>
|
|
|
|
|
#include <cmath>
|
|
|
|
|
#include <numeric>
|
|
|
|
|
#include <boost/container/static_vector.hpp>
|
|
|
|
|
#include <nihstro/shader_bytecode.h>
|
|
|
|
|
#include "common/assert.h"
|
|
|
|
|
#include "common/common_types.h"
|
|
|
|
@ -38,12 +39,42 @@ struct CallStackElement {
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
template <bool Debug>
|
|
|
|
|
void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned offset) {
|
|
|
|
|
void RunInterpreter(const ShaderSetup& setup, UnitState& state, DebugData<Debug>& debug_data,
|
|
|
|
|
unsigned offset) {
|
|
|
|
|
// TODO: Is there a maximal size for this?
|
|
|
|
|
boost::container::static_vector<CallStackElement, 16> call_stack;
|
|
|
|
|
|
|
|
|
|
u32 program_counter = offset;
|
|
|
|
|
|
|
|
|
|
auto call = [&program_counter, &call_stack](u32 offset, u32 num_instructions, u32 return_offset,
|
|
|
|
|
u8 repeat_count, u8 loop_increment) {
|
|
|
|
|
// -1 to make sure when incrementing the PC we end up at the correct offset
|
|
|
|
|
program_counter = offset - 1;
|
|
|
|
|
ASSERT(call_stack.size() < call_stack.capacity());
|
|
|
|
|
call_stack.push_back(
|
|
|
|
|
{offset + num_instructions, return_offset, repeat_count, loop_increment, offset});
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
auto evaluate_condition = [&state](Instruction::FlowControlType flow_control) {
|
|
|
|
|
using Op = Instruction::FlowControlType::Op;
|
|
|
|
|
|
|
|
|
|
bool result_x = flow_control.refx.Value() == state.conditional_code[0];
|
|
|
|
|
bool result_y = flow_control.refy.Value() == state.conditional_code[1];
|
|
|
|
|
|
|
|
|
|
switch (flow_control.op) {
|
|
|
|
|
case Op::Or:
|
|
|
|
|
return result_x || result_y;
|
|
|
|
|
case Op::And:
|
|
|
|
|
return result_x && result_y;
|
|
|
|
|
case Op::JustX:
|
|
|
|
|
return result_x;
|
|
|
|
|
case Op::JustY:
|
|
|
|
|
return result_y;
|
|
|
|
|
default:
|
|
|
|
|
UNREACHABLE();
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
const auto& uniforms = g_state.vs.uniforms;
|
|
|
|
|
const auto& swizzle_data = g_state.vs.swizzle_data;
|
|
|
|
|
const auto& program_code = g_state.vs.program_code;
|
|
|
|
@ -74,20 +105,11 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
const Instruction instr = {program_code[program_counter]};
|
|
|
|
|
const SwizzlePattern swizzle = {swizzle_data[instr.common.operand_desc_id]};
|
|
|
|
|
|
|
|
|
|
auto call = [&program_counter, &call_stack](UnitState<Debug>& state, u32 offset,
|
|
|
|
|
u32 num_instructions, u32 return_offset,
|
|
|
|
|
u8 repeat_count, u8 loop_increment) {
|
|
|
|
|
// -1 to make sure when incrementing the PC we end up at the correct offset
|
|
|
|
|
program_counter = offset - 1;
|
|
|
|
|
ASSERT(call_stack.size() < call_stack.capacity());
|
|
|
|
|
call_stack.push_back(
|
|
|
|
|
{offset + num_instructions, return_offset, repeat_count, loop_increment, offset});
|
|
|
|
|
};
|
|
|
|
|
Record<DebugDataRecord::CUR_INSTR>(state.debug, iteration, program_counter);
|
|
|
|
|
Record<DebugDataRecord::CUR_INSTR>(debug_data, iteration, program_counter);
|
|
|
|
|
if (iteration > 0)
|
|
|
|
|
Record<DebugDataRecord::NEXT_INSTR>(state.debug, iteration - 1, program_counter);
|
|
|
|
|
Record<DebugDataRecord::NEXT_INSTR>(debug_data, iteration - 1, program_counter);
|
|
|
|
|
|
|
|
|
|
state.debug.max_offset = std::max<u32>(state.debug.max_offset, 1 + program_counter);
|
|
|
|
|
debug_data.max_offset = std::max<u32>(debug_data.max_offset, 1 + program_counter);
|
|
|
|
|
|
|
|
|
|
auto LookupSourceRegister = [&](const SourceRegister& source_reg) -> const float24* {
|
|
|
|
|
switch (source_reg.GetRegisterType()) {
|
|
|
|
@ -155,54 +177,54 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
? &state.registers.temporary[instr.common.dest.Value().GetIndex()][0]
|
|
|
|
|
: dummy_vec4_float24;
|
|
|
|
|
|
|
|
|
|
state.debug.max_opdesc_id =
|
|
|
|
|
std::max<u32>(state.debug.max_opdesc_id, 1 + instr.common.operand_desc_id);
|
|
|
|
|
debug_data.max_opdesc_id =
|
|
|
|
|
std::max<u32>(debug_data.max_opdesc_id, 1 + instr.common.operand_desc_id);
|
|
|
|
|
|
|
|
|
|
switch (instr.opcode.Value().EffectiveOpCode()) {
|
|
|
|
|
case OpCode::Id::ADD: {
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
dest[i] = src1[i] + src2[i];
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::MUL: {
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
dest[i] = src1[i] * src2[i];
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::FLR:
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
dest[i] = float24::FromFloat32(std::floor(src1[i].ToFloat32()));
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::MAX:
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
|
continue;
|
|
|
|
@ -212,13 +234,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
// max(NaN, 0) -> 0
|
|
|
|
|
dest[i] = (src1[i] > src2[i]) ? src1[i] : src2[i];
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::MIN:
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
|
continue;
|
|
|
|
@ -228,16 +250,16 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
// min(NaN, 0) -> 0
|
|
|
|
|
dest[i] = (src1[i] < src2[i]) ? src1[i] : src2[i];
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::DP3:
|
|
|
|
|
case OpCode::Id::DP4:
|
|
|
|
|
case OpCode::Id::DPH:
|
|
|
|
|
case OpCode::Id::DPHI: {
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
|
|
|
|
|
OpCode::Id opcode = instr.opcode.Value().EffectiveOpCode();
|
|
|
|
|
if (opcode == OpCode::Id::DPH || opcode == OpCode::Id::DPHI)
|
|
|
|
@ -253,14 +275,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
|
|
|
|
|
dest[i] = dot;
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Reciprocal
|
|
|
|
|
case OpCode::Id::RCP: {
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
float24 rcp_res = float24::FromFloat32(1.0f / src1[0].ToFloat32());
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
@ -268,14 +290,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
|
|
|
|
|
dest[i] = rcp_res;
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Reciprocal Square Root
|
|
|
|
|
case OpCode::Id::RSQ: {
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
float24 rsq_res = float24::FromFloat32(1.0f / std::sqrt(src1[0].ToFloat32()));
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
@ -283,12 +305,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
|
|
|
|
|
dest[i] = rsq_res;
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::MOVA: {
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
for (int i = 0; i < 2; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
|
continue;
|
|
|
|
@ -296,29 +318,29 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
// TODO: Figure out how the rounding is done on hardware
|
|
|
|
|
state.address_registers[i] = static_cast<s32>(src1[i].ToFloat32());
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::ADDR_REG_OUT>(state.debug, iteration,
|
|
|
|
|
Record<DebugDataRecord::ADDR_REG_OUT>(debug_data, iteration,
|
|
|
|
|
state.address_registers);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::MOV: {
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
dest[i] = src1[i];
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::SGE:
|
|
|
|
|
case OpCode::Id::SGEI:
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
|
continue;
|
|
|
|
@ -326,14 +348,14 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
dest[i] = (src1[i] >= src2[i]) ? float24::FromFloat32(1.0f)
|
|
|
|
|
: float24::FromFloat32(0.0f);
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::SLT:
|
|
|
|
|
case OpCode::Id::SLTI:
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
|
continue;
|
|
|
|
@ -341,12 +363,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
dest[i] = (src1[i] < src2[i]) ? float24::FromFloat32(1.0f)
|
|
|
|
|
: float24::FromFloat32(0.0f);
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::CMP:
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
|
|
|
|
for (int i = 0; i < 2; ++i) {
|
|
|
|
|
// TODO: Can you restrict to one compare via dest masking?
|
|
|
|
|
|
|
|
|
@ -383,12 +405,12 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::CMP_RESULT>(state.debug, iteration, state.conditional_code);
|
|
|
|
|
Record<DebugDataRecord::CMP_RESULT>(debug_data, iteration, state.conditional_code);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::EX2: {
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
|
|
|
|
|
// EX2 only takes first component exp2 and writes it to all dest components
|
|
|
|
|
float24 ex2_res = float24::FromFloat32(std::exp2(src1[0].ToFloat32()));
|
|
|
|
@ -399,13 +421,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
dest[i] = ex2_res;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::LG2: {
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
|
|
|
|
|
// LG2 only takes the first component log2 and writes it to all dest components
|
|
|
|
|
float24 lg2_res = float24::FromFloat32(std::log2(src1[0].ToFloat32()));
|
|
|
|
@ -416,7 +438,7 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
dest[i] = lg2_res;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
@ -498,17 +520,17 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
? &state.registers.temporary[instr.mad.dest.Value().GetIndex()][0]
|
|
|
|
|
: dummy_vec4_float24;
|
|
|
|
|
|
|
|
|
|
Record<DebugDataRecord::SRC1>(state.debug, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(state.debug, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::SRC3>(state.debug, iteration, src3);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::SRC1>(debug_data, iteration, src1);
|
|
|
|
|
Record<DebugDataRecord::SRC2>(debug_data, iteration, src2);
|
|
|
|
|
Record<DebugDataRecord::SRC3>(debug_data, iteration, src3);
|
|
|
|
|
Record<DebugDataRecord::DEST_IN>(debug_data, iteration, dest);
|
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
|
|
|
if (!swizzle.DestComponentEnabled(i))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
dest[i] = src1[i] * src2[i] + src3[i];
|
|
|
|
|
}
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(state.debug, iteration, dest);
|
|
|
|
|
Record<DebugDataRecord::DEST_OUT>(debug_data, iteration, dest);
|
|
|
|
|
} else {
|
|
|
|
|
LOG_ERROR(HW_GPU, "Unhandled multiply-add instruction: 0x%02x (%s): 0x%08x",
|
|
|
|
|
(int)instr.opcode.Value().EffectiveOpCode(),
|
|
|
|
@ -518,26 +540,6 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
default: {
|
|
|
|
|
static auto evaluate_condition = [](const UnitState<Debug>& state, bool refx, bool refy,
|
|
|
|
|
Instruction::FlowControlType flow_control) {
|
|
|
|
|
bool results[2] = {refx == state.conditional_code[0],
|
|
|
|
|
refy == state.conditional_code[1]};
|
|
|
|
|
|
|
|
|
|
switch (flow_control.op) {
|
|
|
|
|
case flow_control.Or:
|
|
|
|
|
return results[0] || results[1];
|
|
|
|
|
|
|
|
|
|
case flow_control.And:
|
|
|
|
|
return results[0] && results[1];
|
|
|
|
|
|
|
|
|
|
case flow_control.JustX:
|
|
|
|
|
return results[0];
|
|
|
|
|
|
|
|
|
|
case flow_control.JustY:
|
|
|
|
|
return results[1];
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
// Handle each instruction on its own
|
|
|
|
|
switch (instr.opcode.Value()) {
|
|
|
|
|
case OpCode::Id::END:
|
|
|
|
@ -545,17 +547,15 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::JMPC:
|
|
|
|
|
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration,
|
|
|
|
|
state.conditional_code);
|
|
|
|
|
if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy,
|
|
|
|
|
instr.flow_control)) {
|
|
|
|
|
Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
|
|
|
|
|
if (evaluate_condition(instr.flow_control)) {
|
|
|
|
|
program_counter = instr.flow_control.dest_offset - 1;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::JMPU:
|
|
|
|
|
Record<DebugDataRecord::COND_BOOL_IN>(
|
|
|
|
|
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
|
|
|
|
debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
|
|
|
|
|
|
|
|
|
if (uniforms.b[instr.flow_control.bool_uniform_id] ==
|
|
|
|
|
!(instr.flow_control.num_instructions & 1)) {
|
|
|
|
@ -564,25 +564,23 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::CALL:
|
|
|
|
|
call(state, instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
|
|
|
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
|
|
|
program_counter + 1, 0, 0);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::CALLU:
|
|
|
|
|
Record<DebugDataRecord::COND_BOOL_IN>(
|
|
|
|
|
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
|
|
|
|
debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
|
|
|
|
if (uniforms.b[instr.flow_control.bool_uniform_id]) {
|
|
|
|
|
call(state, instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
|
|
|
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
|
|
|
program_counter + 1, 0, 0);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::CALLC:
|
|
|
|
|
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration,
|
|
|
|
|
state.conditional_code);
|
|
|
|
|
if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy,
|
|
|
|
|
instr.flow_control)) {
|
|
|
|
|
call(state, instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
|
|
|
Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
|
|
|
|
|
if (evaluate_condition(instr.flow_control)) {
|
|
|
|
|
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
|
|
|
program_counter + 1, 0, 0);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
@ -592,14 +590,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
|
|
|
|
|
case OpCode::Id::IFU:
|
|
|
|
|
Record<DebugDataRecord::COND_BOOL_IN>(
|
|
|
|
|
state.debug, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
|
|
|
|
debug_data, iteration, uniforms.b[instr.flow_control.bool_uniform_id]);
|
|
|
|
|
if (uniforms.b[instr.flow_control.bool_uniform_id]) {
|
|
|
|
|
call(state, program_counter + 1,
|
|
|
|
|
instr.flow_control.dest_offset - program_counter - 1,
|
|
|
|
|
call(program_counter + 1, instr.flow_control.dest_offset - program_counter - 1,
|
|
|
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
|
|
|
|
0);
|
|
|
|
|
} else {
|
|
|
|
|
call(state, instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
|
|
|
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
|
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
|
|
|
|
0);
|
|
|
|
|
}
|
|
|
|
@ -609,16 +606,13 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
case OpCode::Id::IFC: {
|
|
|
|
|
// TODO: Do we need to consider swizzlers here?
|
|
|
|
|
|
|
|
|
|
Record<DebugDataRecord::COND_CMP_IN>(state.debug, iteration,
|
|
|
|
|
state.conditional_code);
|
|
|
|
|
if (evaluate_condition(state, instr.flow_control.refx, instr.flow_control.refy,
|
|
|
|
|
instr.flow_control)) {
|
|
|
|
|
call(state, program_counter + 1,
|
|
|
|
|
instr.flow_control.dest_offset - program_counter - 1,
|
|
|
|
|
Record<DebugDataRecord::COND_CMP_IN>(debug_data, iteration, state.conditional_code);
|
|
|
|
|
if (evaluate_condition(instr.flow_control)) {
|
|
|
|
|
call(program_counter + 1, instr.flow_control.dest_offset - program_counter - 1,
|
|
|
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
|
|
|
|
0);
|
|
|
|
|
} else {
|
|
|
|
|
call(state, instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
|
|
|
call(instr.flow_control.dest_offset, instr.flow_control.num_instructions,
|
|
|
|
|
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0,
|
|
|
|
|
0);
|
|
|
|
|
}
|
|
|
|
@ -633,9 +627,8 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
uniforms.i[instr.flow_control.int_uniform_id].w);
|
|
|
|
|
state.address_registers[2] = loop_param.y;
|
|
|
|
|
|
|
|
|
|
Record<DebugDataRecord::LOOP_INT_IN>(state.debug, iteration, loop_param);
|
|
|
|
|
call(state, program_counter + 1,
|
|
|
|
|
instr.flow_control.dest_offset - program_counter + 1,
|
|
|
|
|
Record<DebugDataRecord::LOOP_INT_IN>(debug_data, iteration, loop_param);
|
|
|
|
|
call(program_counter + 1, instr.flow_control.dest_offset - program_counter + 1,
|
|
|
|
|
instr.flow_control.dest_offset + 1, loop_param.x, loop_param.z);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
@ -657,8 +650,8 @@ void RunInterpreter(const ShaderSetup& setup, UnitState<Debug>& state, unsigned
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Explicit instantiation
|
|
|
|
|
template void RunInterpreter(const ShaderSetup& setup, UnitState<false>& state, unsigned offset);
|
|
|
|
|
template void RunInterpreter(const ShaderSetup& setup, UnitState<true>& state, unsigned offset);
|
|
|
|
|
template void RunInterpreter(const ShaderSetup&, UnitState&, DebugData<false>&, unsigned offset);
|
|
|
|
|
template void RunInterpreter(const ShaderSetup&, UnitState&, DebugData<true>&, unsigned offset);
|
|
|
|
|
|
|
|
|
|
} // namespace
|
|
|
|
|
|
|
|
|
|