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@ -106,16 +106,17 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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}
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break;
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}
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case OpCode::Id::LD_L: {
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LOG_DEBUG(HW_GPU, "LD_L cache management mode: {}",
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static_cast<u64>(instr.ld_l.unknown.Value()));
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const auto GetLmem = [&](s32 offset) {
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case OpCode::Id::LD_L:
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LOG_DEBUG(HW_GPU, "LD_L cache management mode: {}", static_cast<u64>(instr.ld_l.unknown));
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[[fallthrough]];
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case OpCode::Id::LD_S: {
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const auto GetMemory = [&](s32 offset) {
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ASSERT(offset % 4 == 0);
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const Node immediate_offset = Immediate(static_cast<s32>(instr.smem_imm) + offset);
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const Node address = Operation(OperationCode::IAdd, NO_PRECISE, GetRegister(instr.gpr8),
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immediate_offset);
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return GetLocalMemory(address);
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return opcode->get().GetId() == OpCode::Id::LD_S ? GetSharedMemory(address)
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: GetLocalMemory(address);
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};
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switch (instr.ldst_sl.type.Value()) {
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@ -135,14 +136,16 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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return 0;
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}
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}();
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for (u32 i = 0; i < count; ++i)
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SetTemporary(bb, i, GetLmem(i * 4));
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for (u32 i = 0; i < count; ++i)
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for (u32 i = 0; i < count; ++i) {
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SetTemporary(bb, i, GetMemory(i * 4));
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}
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for (u32 i = 0; i < count; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
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}
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break;
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}
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default:
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UNIMPLEMENTED_MSG("LD_L Unhandled type: {}",
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UNIMPLEMENTED_MSG("{} Unhandled type: {}", opcode->get().GetName(),
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static_cast<u32>(instr.ldst_sl.type.Value()));
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}
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break;
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