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@ -6478,22 +6478,28 @@ L_stm_s_takeabort:
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const s16 rn_lo = (rn_val & 0xFFFF);
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const s16 rn_hi = ((rn_val >> 16) & 0xFFFF);
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// SMUAD
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if ((instr & 0xf0d0) == 0xf010) {
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state->Reg[rd_idx] = (rn_lo * rm_lo) + (rn_hi * rm_hi);
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const u32 product1 = (rn_lo * rm_lo);
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const u32 product2 = (rn_hi * rm_hi);
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// SMUAD and SMLAD
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if (BIT(6) == 0) {
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state->Reg[rd_idx] = product1 + product2;
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if (BITS(12, 15) != 15) {
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state->Reg[rd_idx] += state->Reg[ra_idx];
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ARMul_AddOverflowQ(state, product1 + product2, state->Reg[ra_idx]);
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}
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ARMul_AddOverflowQ(state, product1, product2);
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}
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// SMUSD
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else if ((instr & 0xf0d0) == 0xf050) {
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state->Reg[rd_idx] = (rn_lo * rm_lo) - (rn_hi * rm_hi);
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}
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// SMLAD
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else if ((instr & 0xd0) == 0x10) {
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state->Reg[rd_idx] = (rn_lo * rm_lo) + (rn_hi * rm_hi) + (s32)state->Reg[ra_idx];
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}
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// SMLSD
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// SMUSD and SMLSD
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else {
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state->Reg[rd_idx] = ((rn_lo * rm_lo) - (rn_hi * rm_hi)) + (s32)state->Reg[ra_idx];
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state->Reg[rd_idx] = product1 - product2;
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if (BITS(12, 15) != 15)
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state->Reg[rd_idx] += state->Reg[ra_idx];
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}
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return 1;
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}
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break;
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