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@ -310,11 +310,22 @@ Id EmitBoundImageWrite(EmitContext&) {
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Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
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Id bias_lc, const IR::Value& offset) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const ImageOperands operands(ctx, info.has_bias != 0, false, info.has_lod_clamp != 0, bias_lc,
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offset);
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return Emit(&EmitContext::OpImageSparseSampleImplicitLod,
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&EmitContext::OpImageSampleImplicitLod, ctx, inst, ctx.F32[4], Texture(ctx, index),
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coords, operands.Mask(), operands.Span());
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if (ctx.stage == Stage::Fragment) {
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const ImageOperands operands(ctx, info.has_bias != 0, false, info.has_lod_clamp != 0,
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bias_lc, offset);
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return Emit(&EmitContext::OpImageSparseSampleImplicitLod,
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&EmitContext::OpImageSampleImplicitLod, ctx, inst, ctx.F32[4],
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Texture(ctx, index), coords, operands.Mask(), operands.Span());
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} else {
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// We can't use implicit lods on non-fragment stages on SPIR-V. Maxwell hardware behaves as
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// if the lod was explicitly zero. This may change on Turing with implicit compute
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// derivatives
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const Id lod{ctx.Const(0)};
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const ImageOperands operands(ctx, false, true, info.has_lod_clamp != 0, lod, offset);
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return Emit(&EmitContext::OpImageSparseSampleExplicitLod,
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&EmitContext::OpImageSampleExplicitLod, ctx, inst, ctx.F32[4],
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Texture(ctx, index), coords, operands.Mask(), operands.Span());
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}
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}
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Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
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