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@ -2053,7 +2053,37 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(pld)(unsigned int inst, int index)
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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inst_base->cond = BITS(inst, 28, 31);
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inst_base->idx = index;
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inst_base->br = NON_BRANCH;
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inst_base->load_r15 = 0;
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inst_cream->op1 = BITS(inst, 21, 22);
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inst_cream->Rm = BITS(inst, 0, 3);
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inst_cream->Rn = BITS(inst, 16, 19);
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inst_cream->Rd = BITS(inst, 12, 15);
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return inst_base;
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qadd8)(unsigned int inst, int index)
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{
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arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(generic_arm_inst));
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@ -2080,9 +2110,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(qaddsubx)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd8)(inst, index);
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}
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdadd)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDADD"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qdsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QDSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("QSUB"); }
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ARM_INST_PTR INTERPRETER_TRANSLATE(qsub8)(unsigned int inst, int index)
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{
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return INTERPRETER_TRANSLATE(qadd8)(inst, index);
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@ -5042,6 +5069,78 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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}
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QADD_INST:
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QDADD_INST:
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QDSUB_INST:
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QSUB_INST:
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{
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
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generic_arm_inst* const inst_cream = (generic_arm_inst*)inst_base->component;
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const u8 op1 = inst_cream->op1;
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const u32 rm_val = RM;
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const u32 rn_val = RN;
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u32 result = 0;
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// QADD
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if (op1 == 0x00) {
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result = rm_val + rn_val;
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if (AddOverflow(rm_val, rn_val, result)) {
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result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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}
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// QSUB
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else if (op1 == 0x01) {
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result = rm_val - rn_val;
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if (SubOverflow(rm_val, rn_val, result)) {
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result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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}
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// QDADD
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else if (op1 == 0x02) {
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u32 mul = (rn_val * 2);
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if (AddOverflow(rn_val, rn_val, rn_val * 2)) {
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mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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result = mul + rm_val;
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if (AddOverflow(rm_val, mul, result)) {
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result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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}
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// QDSUB
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else if (op1 == 0x03) {
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u32 mul = (rn_val * 2);
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if (AddOverflow(rn_val, rn_val, mul)) {
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mul = POS(mul) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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result = rm_val - mul;
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if (SubOverflow(rm_val, mul, result)) {
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result = POS(result) ? 0x80000000 : 0x7FFFFFFF;
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cpu->Cpsr |= (1 << 27);
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}
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}
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RD = result;
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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INC_PC(sizeof(generic_arm_inst));
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FETCH_INST;
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GOTO_NEXT_INST;
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}
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QADD8_INST:
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QADD16_INST:
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QADDSUBX_INST:
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@ -5104,10 +5203,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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GOTO_NEXT_INST;
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}
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QDADD_INST:
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QDSUB_INST:
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QSUB_INST:
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REV_INST:
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REV16_INST:
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REVSH_INST:
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