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@ -99,7 +99,8 @@ struct Regs {
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TEXCOORD1_U = 14,
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TEXCOORD1_V = 15,
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// TODO: Not verified
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TEXCOORD0_W = 16,
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VIEW_X = 18,
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VIEW_Y = 19,
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VIEW_Z = 20,
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@ -871,7 +872,7 @@ struct Regs {
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LightSrc light[8];
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LightColor global_ambient; // Emission + (material.ambient * lighting.ambient)
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INSERT_PADDING_WORDS(0x1);
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BitField<0, 3, u32> num_lights; // Number of enabled lights - 1
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BitField<0, 3, u32> max_light_index; // Number of enabled lights - 1
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union {
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BitField<2, 2, LightingFresnelSelector> fresnel_selector;
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@ -1048,7 +1049,7 @@ struct Regs {
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BitField<48, 12, u64> attribute_mask;
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// number of total attributes minus 1
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BitField<60, 4, u64> num_extra_attributes;
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BitField<60, 4, u64> max_attribute_index;
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};
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inline VertexAttributeFormat GetFormat(int n) const {
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@ -1079,7 +1080,7 @@ struct Regs {
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}
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inline int GetNumTotalAttributes() const {
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return (int)num_extra_attributes + 1;
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return (int)max_attribute_index + 1;
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}
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// Attribute loaders map the source vertex data to input attributes
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@ -1179,7 +1180,12 @@ struct Regs {
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}
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} command_buffer;
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INSERT_PADDING_WORDS(0x07);
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INSERT_PADDING_WORDS(4);
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/// Number of input attributes to the vertex shader minus 1
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BitField<0, 4, u32> max_input_attrib_index;
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INSERT_PADDING_WORDS(2);
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enum class GPUMode : u32 {
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Drawing = 0,
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@ -1217,42 +1223,21 @@ struct Regs {
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union {
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// Number of input attributes to shader unit - 1
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BitField<0, 4, u32> num_input_attributes;
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BitField<0, 4, u32> max_input_attribute_index;
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};
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// Offset to shader program entry point (in words)
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BitField<0, 16, u32> main_offset;
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union {
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BitField<0, 4, u64> attribute0_register;
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BitField<4, 4, u64> attribute1_register;
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BitField<8, 4, u64> attribute2_register;
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BitField<12, 4, u64> attribute3_register;
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BitField<16, 4, u64> attribute4_register;
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BitField<20, 4, u64> attribute5_register;
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BitField<24, 4, u64> attribute6_register;
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BitField<28, 4, u64> attribute7_register;
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BitField<32, 4, u64> attribute8_register;
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BitField<36, 4, u64> attribute9_register;
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BitField<40, 4, u64> attribute10_register;
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BitField<44, 4, u64> attribute11_register;
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BitField<48, 4, u64> attribute12_register;
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BitField<52, 4, u64> attribute13_register;
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BitField<56, 4, u64> attribute14_register;
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BitField<60, 4, u64> attribute15_register;
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/// Maps input attributes to registers. 4-bits per attribute, specifying a register index
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u32 input_attribute_to_register_map_low;
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u32 input_attribute_to_register_map_high;
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int GetRegisterForAttribute(int attribute_index) const {
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u64 fields[] = {
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attribute0_register, attribute1_register, attribute2_register,
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attribute3_register, attribute4_register, attribute5_register,
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attribute6_register, attribute7_register, attribute8_register,
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attribute9_register, attribute10_register, attribute11_register,
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attribute12_register, attribute13_register, attribute14_register,
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attribute15_register,
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};
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return (int)fields[attribute_index];
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}
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} input_register_map;
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unsigned int GetRegisterForAttribute(unsigned int attribute_index) const {
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u64 map = ((u64)input_attribute_to_register_map_high << 32) |
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(u64)input_attribute_to_register_map_low;
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return (map >> (attribute_index * 4)) & 0b1111;
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}
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BitField<0, 16, u32> output_mask;
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