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@ -160,60 +160,72 @@ void TriggerCmdReqQueue(Service::Interface* self) {
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};
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GX_CmdBufferHeader* header = (GX_CmdBufferHeader*)GX_GetCmdBufferPointer(g_thread_id);
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u32* cmd_buff = (u32*)GX_GetCmdBufferPointer(g_thread_id, 0x20 + (header->index * 0x20));
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auto& command = *(const GXCommand*)GX_GetCmdBufferPointer(g_thread_id, 0x20 + (header->index * 0x20));
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switch (static_cast<GXCommandId>(cmd_buff[0])) {
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switch (command.id) {
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// GX request DMA - typically used for copying memory from GSP heap to VRAM
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case GXCommandId::REQUEST_DMA:
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memcpy(Memory::GetPointer(cmd_buff[2]), Memory::GetPointer(cmd_buff[1]), cmd_buff[3]);
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memcpy(Memory::GetPointer(command.dma_request.dest_address),
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Memory::GetPointer(command.dma_request.source_address),
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command.dma_request.size);
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break;
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case GXCommandId::SET_COMMAND_LIST_LAST:
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WriteGPURegister(GPU::Regs::CommandProcessor + 2, cmd_buff[1] >> 3); // command list data address
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WriteGPURegister(GPU::Regs::CommandProcessor, cmd_buff[2] >> 3); // command list address
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WriteGPURegister(GPU::Regs::CommandProcessor + 4, 1); // TODO: Not sure if we are supposed to always write this .. seems to trigger processing though
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{
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auto& params = command.set_command_list_last;
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WriteGPURegister(GPU::Regs::CommandProcessor + 2, params.address >> 3);
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WriteGPURegister(GPU::Regs::CommandProcessor, params.size >> 3);
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WriteGPURegister(GPU::Regs::CommandProcessor + 4, 1); // TODO: Not sure if we are supposed to always write this .. seems to trigger processing though
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// TODO: Move this to GPU
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// TODO: Not sure what units the size is measured in
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g_debugger.CommandListCalled(cmd_buff[1], (u32*)Memory::GetPointer(cmd_buff[1]), cmd_buff[2]);
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g_debugger.CommandListCalled(params.address,
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(u32*)Memory::GetPointer(params.address),
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params.size);
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break;
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}
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case GXCommandId::SET_MEMORY_FILL:
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WriteGPURegister(GPU::Regs::MemoryFill, cmd_buff[1] >> 3); // Start 1
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WriteGPURegister(GPU::Regs::MemoryFill + 1, cmd_buff[3] >> 3); // End 1
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WriteGPURegister(GPU::Regs::MemoryFill + 2, cmd_buff[3] - cmd_buff[1]); // Size 1
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WriteGPURegister(GPU::Regs::MemoryFill + 3, cmd_buff[2]); // Value 1
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{
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auto& params = command.memory_fill;
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WriteGPURegister(GPU::Regs::MemoryFill, params.start1 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 1, params.end1 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 2, params.end1 - params.start1);
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WriteGPURegister(GPU::Regs::MemoryFill + 3, params.value1);
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WriteGPURegister(GPU::Regs::MemoryFill + 4, cmd_buff[4] >> 3); // Start 2
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WriteGPURegister(GPU::Regs::MemoryFill + 5, cmd_buff[6] >> 3); // End 2
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WriteGPURegister(GPU::Regs::MemoryFill + 6, cmd_buff[6] - cmd_buff[4]); // Size 2
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WriteGPURegister(GPU::Regs::MemoryFill + 7, cmd_buff[5]); // Value 2
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WriteGPURegister(GPU::Regs::MemoryFill + 4, params.start2 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 5, params.end2 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 6, params.end2 - params.start2);
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WriteGPURegister(GPU::Regs::MemoryFill + 7, params.value2);
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break;
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}
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// TODO: Check if texture copies are implemented correctly..
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case GXCommandId::SET_DISPLAY_TRANSFER:
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case GXCommandId::SET_TEXTURE_COPY:
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WriteGPURegister(GPU::Regs::DisplayTransfer, cmd_buff[1] >> 3); // input buffer address
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WriteGPURegister(GPU::Regs::DisplayTransfer + 1, cmd_buff[2] >> 3); // output buffer address
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WriteGPURegister(GPU::Regs::DisplayTransfer + 3, cmd_buff[3]); // input buffer size
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WriteGPURegister(GPU::Regs::DisplayTransfer + 2, cmd_buff[4]); // output buffer size
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WriteGPURegister(GPU::Regs::DisplayTransfer + 4, cmd_buff[5]); // transfer flags
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{
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auto& params = command.image_copy;
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WriteGPURegister(GPU::Regs::DisplayTransfer, params.in_buffer_address >> 3);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 1, params.out_buffer_address >> 3);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 3, params.in_buffer_size);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 2, params.out_buffer_size);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 4, params.flags);
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// TODO: Should this only be ORed with 1 for texture copies?
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WriteGPURegister(GPU::Regs::DisplayTransfer + 6, 1); // trigger transfer
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// trigger transfer
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WriteGPURegister(GPU::Regs::DisplayTransfer + 6, 1);
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break;
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}
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case GXCommandId::SET_COMMAND_LIST_FIRST:
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{
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//u32* buf0_data = (u32*)Memory::GetPointer(cmd_buff[1]);
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//u32* buf1_data = (u32*)Memory::GetPointer(cmd_buff[3]);
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//u32* buf2_data = (u32*)Memory::GetPointer(cmd_buff[5]);
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// TODO
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break;
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}
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default:
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ERROR_LOG(GSP, "unknown command 0x%08X", cmd_buff[0]);
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ERROR_LOG(GSP, "unknown command 0x%08X", (int)command.id.Value());
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}
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GX_FinishCommand(g_thread_id);
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