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@ -261,6 +261,19 @@ union Instruction {
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BitField<50, 1, u64> saturate_a;
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} conversion;
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union {
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BitField<31, 4, u64> component_mask;
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bool IsComponentEnabled(size_t component) const {
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return ((1 << component) & component_mask) != 0;
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}
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} tex;
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union {
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// TODO(bunnei): This is just a guess, needs to be verified
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BitField<52, 1, u64> enable_g_component;
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} texs;
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BitField<61, 1, u64> is_b_imm;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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@ -281,6 +294,7 @@ public:
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KIL,
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LD_A,
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ST_A,
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TEX,
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TEXQ, // Texture Query
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TEXS, // Texture Fetch with scalar/non-vec4 source/destinations
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TLDS, // Texture Load with scalar/non-vec4 source/destinations
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@ -444,6 +458,7 @@ private:
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INST("111000110011----", Id::KIL, Type::Flow, "KIL"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
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INST("1100000000111---", Id::TEX, Type::Memory, "TEX"),
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INST("1101111101001---", Id::TEXQ, Type::Memory, "TEXQ"),
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INST("1101100---------", Id::TEXS, Type::Memory, "TEXS"),
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INST("1101101---------", Id::TLDS, Type::Memory, "TLDS"),
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