core: Implement separate A32/A64 ARM interfaces.
bunnei
parent
6fc485a607
commit
c083ea7d78
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// Copyright 2020 yuzu emulator team
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cinttypes>
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#include <memory>
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#include <dynarmic/A32/a32.h>
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#include <dynarmic/A32/config.h>
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#include <dynarmic/A32/context.h>
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#include "common/microprofile.h"
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#include "core/arm/dynarmic/arm_dynarmic_32.h"
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#include "core/arm/dynarmic/arm_dynarmic_64.h"
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#include "core/arm/dynarmic/arm_dynarmic_cp15.h"
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#include "core/core.h"
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#include "core/core_manager.h"
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#include "core/core_timing.h"
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#include "core/hle/kernel/svc.h"
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#include "core/memory.h"
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namespace Core {
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class DynarmicCallbacks32 : public Dynarmic::A32::UserCallbacks {
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public:
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explicit DynarmicCallbacks32(ARM_Dynarmic_32& parent) : parent(parent) {}
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u8 MemoryRead8(u32 vaddr) override {
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return parent.system.Memory().Read8(vaddr);
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}
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u16 MemoryRead16(u32 vaddr) override {
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return parent.system.Memory().Read16(vaddr);
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}
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u32 MemoryRead32(u32 vaddr) override {
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return parent.system.Memory().Read32(vaddr);
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}
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u64 MemoryRead64(u32 vaddr) override {
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return parent.system.Memory().Read64(vaddr);
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}
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void MemoryWrite8(u32 vaddr, u8 value) override {
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parent.system.Memory().Write8(vaddr, value);
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}
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void MemoryWrite16(u32 vaddr, u16 value) override {
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parent.system.Memory().Write16(vaddr, value);
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}
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void MemoryWrite32(u32 vaddr, u32 value) override {
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parent.system.Memory().Write32(vaddr, value);
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}
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void MemoryWrite64(u32 vaddr, u64 value) override {
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parent.system.Memory().Write64(vaddr, value);
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}
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void InterpreterFallback(u32 pc, std::size_t num_instructions) override {
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UNIMPLEMENTED();
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}
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void ExceptionRaised(u32 pc, Dynarmic::A32::Exception exception) override {
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switch (exception) {
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case Dynarmic::A32::Exception::UndefinedInstruction:
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case Dynarmic::A32::Exception::UnpredictableInstruction:
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break;
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case Dynarmic::A32::Exception::Breakpoint:
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break;
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}
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LOG_CRITICAL(HW_GPU, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
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static_cast<std::size_t>(exception), pc, MemoryReadCode(pc));
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UNIMPLEMENTED();
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}
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void CallSVC(u32 swi) override {
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Kernel::CallSVC(parent.system, swi);
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}
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void AddTicks(u64 ticks) override {
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// Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
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// rough approximation of the amount of executed ticks in the system, it may be thrown off
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// if not all cores are doing a similar amount of work. Instead of doing this, we should
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// device a way so that timing is consistent across all cores without increasing the ticks 4
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// times.
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u64 amortized_ticks = (ticks - num_interpreted_instructions) / Core::NUM_CPU_CORES;
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// Always execute at least one tick.
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amortized_ticks = std::max<u64>(amortized_ticks, 1);
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parent.system.CoreTiming().AddTicks(amortized_ticks);
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num_interpreted_instructions = 0;
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}
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u64 GetTicksRemaining() override {
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return std::max(parent.system.CoreTiming().GetDowncount(), {});
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}
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ARM_Dynarmic_32& parent;
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std::size_t num_interpreted_instructions{};
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u64 tpidrro_el0{};
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u64 tpidr_el0{};
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};
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std::shared_ptr<Dynarmic::A32::Jit> ARM_Dynarmic_32::MakeJit(Common::PageTable& page_table,
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std::size_t address_space_bits) const {
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Dynarmic::A32::UserConfig config;
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config.callbacks = cb.get();
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// TODO(bunnei): Implement page table for 32-bit
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// config.page_table = &page_table.pointers;
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config.coprocessors[15] = std::make_shared<DynarmicCP15>((u32*)&CP15_regs[0]);
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config.define_unpredictable_behaviour = true;
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return std::make_unique<Dynarmic::A32::Jit>(config);
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}
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MICROPROFILE_DEFINE(ARM_Jit_Dynarmic_32, "ARM JIT", "Dynarmic", MP_RGB(255, 64, 64));
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void ARM_Dynarmic_32::Run() {
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MICROPROFILE_SCOPE(ARM_Jit_Dynarmic_32);
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jit->Run();
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}
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void ARM_Dynarmic_32::Step() {
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cb->InterpreterFallback(jit->Regs()[15], 1);
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}
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ARM_Dynarmic_32::ARM_Dynarmic_32(System& system, ExclusiveMonitor& exclusive_monitor,
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std::size_t core_index)
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: ARM_Interface{system},
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cb(std::make_unique<DynarmicCallbacks32>(*this)), core_index{core_index},
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exclusive_monitor{dynamic_cast<DynarmicExclusiveMonitor&>(exclusive_monitor)} {}
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ARM_Dynarmic_32::~ARM_Dynarmic_32() = default;
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void ARM_Dynarmic_32::SetPC(u64 pc) {
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jit->Regs()[15] = static_cast<u32>(pc);
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}
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u64 ARM_Dynarmic_32::GetPC() const {
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return jit->Regs()[15];
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}
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u64 ARM_Dynarmic_32::GetReg(int index) const {
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return jit->Regs()[index];
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}
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void ARM_Dynarmic_32::SetReg(int index, u64 value) {
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jit->Regs()[index] = static_cast<u32>(value);
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}
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u128 ARM_Dynarmic_32::GetVectorReg(int index) const {
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return {};
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}
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void ARM_Dynarmic_32::SetVectorReg(int index, u128 value) {}
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u32 ARM_Dynarmic_32::GetPSTATE() const {
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return jit->Cpsr();
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}
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void ARM_Dynarmic_32::SetPSTATE(u32 cpsr) {
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jit->SetCpsr(cpsr);
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}
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u64 ARM_Dynarmic_32::GetTlsAddress() const {
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return CP15_regs[static_cast<std::size_t>(CP15Register::CP15_THREAD_URO)];
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}
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void ARM_Dynarmic_32::SetTlsAddress(VAddr address) {
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CP15_regs[static_cast<std::size_t>(CP15Register::CP15_THREAD_URO)] = static_cast<u32>(address);
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}
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u64 ARM_Dynarmic_32::GetTPIDR_EL0() const {
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return cb->tpidr_el0;
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}
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void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
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cb->tpidr_el0 = value;
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}
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void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
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Dynarmic::A32::Context context;
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jit->SaveContext(context);
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ctx.cpu_registers = context.Regs();
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ctx.cpsr = context.Cpsr();
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}
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void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
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Dynarmic::A32::Context context;
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context.Regs() = ctx.cpu_registers;
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context.SetCpsr(ctx.cpsr);
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jit->LoadContext(context);
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}
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void ARM_Dynarmic_32::PrepareReschedule() {
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jit->HaltExecution();
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}
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void ARM_Dynarmic_32::ClearInstructionCache() {
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jit->ClearCache();
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}
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void ARM_Dynarmic_32::ClearExclusiveState() {}
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void ARM_Dynarmic_32::PageTableChanged(Common::PageTable& page_table,
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std::size_t new_address_space_size_in_bits) {
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auto key = std::make_pair(&page_table, new_address_space_size_in_bits);
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auto iter = jit_cache.find(key);
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if (iter != jit_cache.end()) {
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jit = iter->second;
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return;
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}
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jit = MakeJit(page_table, new_address_space_size_in_bits);
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jit_cache.emplace(key, jit);
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}
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} // namespace Core
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@ -0,0 +1,77 @@
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// Copyright 2020 yuzu emulator team
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <memory>
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#include <unordered_map>
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#include <dynarmic/A32/a32.h>
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#include <dynarmic/A64/a64.h>
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#include <dynarmic/A64/exclusive_monitor.h>
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#include "common/common_types.h"
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#include "common/hash.h"
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#include "core/arm/arm_interface.h"
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#include "core/arm/exclusive_monitor.h"
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namespace Memory {
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class Memory;
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}
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namespace Core {
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class DynarmicCallbacks32;
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class DynarmicExclusiveMonitor;
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class System;
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class ARM_Dynarmic_32 final : public ARM_Interface {
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public:
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ARM_Dynarmic_32(System& system, ExclusiveMonitor& exclusive_monitor, std::size_t core_index);
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~ARM_Dynarmic_32() override;
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void SetPC(u64 pc) override;
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u64 GetPC() const override;
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u64 GetReg(int index) const override;
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void SetReg(int index, u64 value) override;
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u128 GetVectorReg(int index) const override;
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void SetVectorReg(int index, u128 value) override;
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u32 GetPSTATE() const override;
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void SetPSTATE(u32 pstate) override;
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void Run() override;
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void Step() override;
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VAddr GetTlsAddress() const override;
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void SetTlsAddress(VAddr address) override;
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void SetTPIDR_EL0(u64 value) override;
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u64 GetTPIDR_EL0() const override;
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void SaveContext(ThreadContext32& ctx) override;
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void SaveContext(ThreadContext64& ctx) override {}
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void LoadContext(const ThreadContext32& ctx) override;
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void LoadContext(const ThreadContext64& ctx) override {}
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void PrepareReschedule() override;
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void ClearExclusiveState() override;
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void ClearInstructionCache() override;
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void PageTableChanged(Common::PageTable& new_page_table,
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std::size_t new_address_space_size_in_bits) override;
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private:
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std::shared_ptr<Dynarmic::A32::Jit> MakeJit(Common::PageTable& page_table,
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std::size_t address_space_bits) const;
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using JitCacheKey = std::pair<Common::PageTable*, std::size_t>;
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using JitCacheType =
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std::unordered_map<JitCacheKey, std::shared_ptr<Dynarmic::A32::Jit>, Common::PairHash>;
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friend class DynarmicCallbacks32;
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std::unique_ptr<DynarmicCallbacks32> cb;
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JitCacheType jit_cache;
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std::shared_ptr<Dynarmic::A32::Jit> jit;
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std::size_t core_index;
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DynarmicExclusiveMonitor& exclusive_monitor;
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std::array<u32, 84> CP15_regs{};
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};
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} // namespace Core
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