Pica: Add vertex shader implementation.
Tony Wasserka
parent
d443f0a921
commit
c526512619
@ -0,0 +1,270 @@
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// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include "pica.h"
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#include "vertex_shader.h"
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#include <core/mem_map.h>
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#include <common/file_util.h>
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namespace Pica {
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namespace VertexShader {
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static struct {
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Math::Vec4<float24> f[96];
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} shader_uniforms;
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// TODO: Not sure where the shader binary and swizzle patterns are supposed to be loaded to!
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// For now, we just keep these local arrays around.
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static u32 shader_memory[1024];
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static u32 swizzle_data[1024];
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void SubmitShaderMemoryChange(u32 addr, u32 value)
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{
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shader_memory[addr] = value;
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}
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void SubmitSwizzleDataChange(u32 addr, u32 value)
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{
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swizzle_data[addr] = value;
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}
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Math::Vec4<float24>& GetFloatUniform(u32 index)
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{
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return shader_uniforms.f[index];
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}
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struct VertexShaderState {
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u32* program_counter;
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const float24* input_register_table[16];
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float24* output_register_table[7*4];
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Math::Vec4<float24> temporary_registers[16];
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bool status_registers[2];
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enum {
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INVALID_ADDRESS = 0xFFFFFFFF
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};
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u32 call_stack[8]; // TODO: What is the maximal call stack depth?
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u32* call_stack_pointer;
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};
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static void ProcessShaderCode(VertexShaderState& state) {
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while (true) {
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bool increment_pc = true;
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bool exit_loop = false;
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const Instruction& instr = *(const Instruction*)state.program_counter;
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const float24* src1_ = (instr.common.src1 < 0x10) ? state.input_register_table[instr.common.src1]
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: (instr.common.src1 < 0x20) ? &state.temporary_registers[instr.common.src1-0x10].x
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: (instr.common.src1 < 0x80) ? &shader_uniforms.f[instr.common.src1-0x20].x
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: nullptr;
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const float24* src2_ = (instr.common.src2 < 0x10) ? state.input_register_table[instr.common.src2]
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: &state.temporary_registers[instr.common.src2-0x10].x;
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// TODO: Unsure about the limit values
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float24* dest = (instr.common.dest <= 0x1C) ? state.output_register_table[instr.common.dest]
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: (instr.common.dest <= 0x3C) ? nullptr
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: (instr.common.dest <= 0x7C) ? &state.temporary_registers[(instr.common.dest-0x40)/4][instr.common.dest%4]
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: nullptr;
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.common.operand_desc_id];
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const float24 src1[4] = {
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src1_[(int)swizzle.GetSelectorSrc1(0)],
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src1_[(int)swizzle.GetSelectorSrc1(1)],
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src1_[(int)swizzle.GetSelectorSrc1(2)],
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src1_[(int)swizzle.GetSelectorSrc1(3)],
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};
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const float24 src2[4] = {
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src2_[(int)swizzle.GetSelectorSrc2(0)],
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src2_[(int)swizzle.GetSelectorSrc2(1)],
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src2_[(int)swizzle.GetSelectorSrc2(2)],
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src2_[(int)swizzle.GetSelectorSrc2(3)],
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};
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switch (instr.opcode) {
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case Instruction::OpCode::ADD:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i] + src2[i];
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}
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break;
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}
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case Instruction::OpCode::MUL:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i] * src2[i];
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}
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break;
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}
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case Instruction::OpCode::DP3:
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case Instruction::OpCode::DP4:
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{
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float24 dot = float24::FromFloat32(0.f);
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int num_components = (instr.opcode == Instruction::OpCode::DP3) ? 3 : 4;
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for (int i = 0; i < num_components; ++i)
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dot = dot + src1[i] * src2[i];
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for (int i = 0; i < num_components; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = dot;
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}
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break;
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}
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// Reciprocal
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case Instruction::OpCode::RCP:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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// TODO: Be stable against division by zero!
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// TODO: I think this might be wrong... we should only use one component here
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dest[i] = float24::FromFloat32(1.0 / src1[i].ToFloat32());
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}
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break;
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}
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// Reciprocal Square Root
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case Instruction::OpCode::RSQ:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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// TODO: Be stable against division by zero!
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// TODO: I think this might be wrong... we should only use one component here
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dest[i] = float24::FromFloat32(1.0 / sqrt(src1[i].ToFloat32()));
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}
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break;
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}
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case Instruction::OpCode::MOV:
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{
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for (int i = 0; i < 4; ++i) {
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if (!swizzle.DestComponentEnabled(i))
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continue;
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dest[i] = src1[i];
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}
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break;
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}
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case Instruction::OpCode::RET:
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if (*state.call_stack_pointer == VertexShaderState::INVALID_ADDRESS) {
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exit_loop = true;
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} else {
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state.program_counter = &shader_memory[*state.call_stack_pointer--];
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*state.call_stack_pointer = VertexShaderState::INVALID_ADDRESS;
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}
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break;
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case Instruction::OpCode::CALL:
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increment_pc = false;
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_dbg_assert_(GPU, state.call_stack_pointer - state.call_stack < sizeof(state.call_stack));
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*++state.call_stack_pointer = state.program_counter - shader_memory;
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// TODO: Does this offset refer to the beginning of shader memory?
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state.program_counter = &shader_memory[instr.flow_control.offset_words];
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break;
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case Instruction::OpCode::FLS:
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// TODO: Do whatever needs to be done here?
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break;
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default:
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ERROR_LOG(GPU, "Unhandled instruction: 0x%02x (%s): 0x%08x",
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(int)instr.opcode.Value(), instr.GetOpCodeName().c_str(), instr.hex);
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break;
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}
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if (increment_pc)
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++state.program_counter;
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if (exit_loop)
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break;
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}
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}
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OutputVertex RunShader(const InputVertex& input, int num_attributes)
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{
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VertexShaderState state;
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const u32* main = &shader_memory[registers.vs_main_offset];
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state.program_counter = (u32*)main;
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// Setup input register table
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const auto& attribute_register_map = registers.vs_input_register_map;
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float24 dummy_register;
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std::fill(&state.input_register_table[0], &state.input_register_table[16], &dummy_register);
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if(num_attributes > 0) state.input_register_table[attribute_register_map.attribute0_register] = &input.attr[0].x;
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if(num_attributes > 1) state.input_register_table[attribute_register_map.attribute1_register] = &input.attr[1].x;
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if(num_attributes > 2) state.input_register_table[attribute_register_map.attribute2_register] = &input.attr[2].x;
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if(num_attributes > 3) state.input_register_table[attribute_register_map.attribute3_register] = &input.attr[3].x;
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if(num_attributes > 4) state.input_register_table[attribute_register_map.attribute4_register] = &input.attr[4].x;
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if(num_attributes > 5) state.input_register_table[attribute_register_map.attribute5_register] = &input.attr[5].x;
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if(num_attributes > 6) state.input_register_table[attribute_register_map.attribute6_register] = &input.attr[6].x;
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if(num_attributes > 7) state.input_register_table[attribute_register_map.attribute7_register] = &input.attr[7].x;
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if(num_attributes > 8) state.input_register_table[attribute_register_map.attribute8_register] = &input.attr[8].x;
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if(num_attributes > 9) state.input_register_table[attribute_register_map.attribute9_register] = &input.attr[9].x;
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if(num_attributes > 10) state.input_register_table[attribute_register_map.attribute10_register] = &input.attr[10].x;
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if(num_attributes > 11) state.input_register_table[attribute_register_map.attribute11_register] = &input.attr[11].x;
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if(num_attributes > 12) state.input_register_table[attribute_register_map.attribute12_register] = &input.attr[12].x;
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if(num_attributes > 13) state.input_register_table[attribute_register_map.attribute13_register] = &input.attr[13].x;
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if(num_attributes > 14) state.input_register_table[attribute_register_map.attribute14_register] = &input.attr[14].x;
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if(num_attributes > 15) state.input_register_table[attribute_register_map.attribute15_register] = &input.attr[15].x;
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// Setup output register table
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OutputVertex ret;
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for (int i = 0; i < 7; ++i) {
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const auto& output_register_map = registers.vs_output_attributes[i];
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u32 semantics[4] = {
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_z, output_register_map.map_w
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};
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for (int comp = 0; comp < 4; ++comp)
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state.output_register_table[4*i+comp] = ((float24*)&ret) + semantics[comp];
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}
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state.status_registers[0] = false;
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state.status_registers[1] = false;
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std::fill(state.call_stack, state.call_stack + sizeof(state.call_stack) / sizeof(state.call_stack[0]),
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VertexShaderState::INVALID_ADDRESS);
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state.call_stack_pointer = &state.call_stack[0];
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ProcessShaderCode(state);
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DEBUG_LOG(GPU, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
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ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
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ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32());
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return ret;
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}
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} // namespace
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} // namespace
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@ -0,0 +1,211 @@
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// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include <initializer_list>
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#include <common/common_types.h>
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#include "math.h"
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#include "pica.h"
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namespace Pica {
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namespace VertexShader {
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struct InputVertex {
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Math::Vec4<float24> attr[16];
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};
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struct OutputVertex {
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OutputVertex() = default;
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// VS output attributes
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Math::Vec4<float24> pos;
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Math::Vec4<float24> dummy; // quaternions (not implemented, yet)
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Math::Vec4<float24> color;
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Math::Vec2<float24> tc0;
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float24 tc0_v;
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// Padding for optimal alignment
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float24 pad[14];
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// Attributes used to store intermediate results
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// position after perspective divide
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Math::Vec3<float24> screenpos;
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// Linear interpolation
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// factor: 0=this, 1=vtx
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void Lerp(float24 factor, const OutputVertex& vtx) {
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pos = pos * factor + vtx.pos * (float24::FromFloat32(1) - factor);
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// TODO: Should perform perspective correct interpolation here...
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tc0 = tc0 * factor + vtx.tc0 * (float24::FromFloat32(1) - factor);
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screenpos = screenpos * factor + vtx.screenpos * (float24::FromFloat32(1) - factor);
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color = color * factor + vtx.color * (float24::FromFloat32(1) - factor);
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}
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// Linear interpolation
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// factor: 0=v0, 1=v1
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static OutputVertex Lerp(float24 factor, const OutputVertex& v0, const OutputVertex& v1) {
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OutputVertex ret = v0;
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ret.Lerp(factor, v1);
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return ret;
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}
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};
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static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
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union Instruction {
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enum class OpCode : u32 {
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ADD = 0x0,
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DP3 = 0x1,
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DP4 = 0x2,
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MUL = 0x8,
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MAX = 0xC,
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MIN = 0xD,
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RCP = 0xE,
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RSQ = 0xF,
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MOV = 0x13,
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RET = 0x21,
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FLS = 0x22, // Flush
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CALL = 0x24,
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};
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std::string GetOpCodeName() const {
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std::map<OpCode, std::string> map = {
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{ OpCode::ADD, "ADD" },
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{ OpCode::DP3, "DP3" },
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{ OpCode::DP4, "DP4" },
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{ OpCode::MUL, "MUL" },
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{ OpCode::MAX, "MAX" },
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{ OpCode::MIN, "MIN" },
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{ OpCode::RCP, "RCP" },
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{ OpCode::RSQ, "RSQ" },
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{ OpCode::MOV, "MOV" },
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{ OpCode::RET, "RET" },
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{ OpCode::FLS, "FLS" },
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};
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auto it = map.find(opcode);
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if (it == map.end())
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return "UNK";
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else
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return it->second;
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}
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u32 hex;
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BitField<0x1a, 0x6, OpCode> opcode;
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// General notes:
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//
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// When two input registers are used, one of them uses a 5-bit index while the other
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// one uses a 7-bit index. This is because at most one floating point uniform may be used
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// as an input.
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// Format used e.g. by arithmetic instructions and comparisons
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// "src1" and "src2" specify register indices (i.e. indices referring to groups of 4 floats),
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// while "dest" addresses individual floats.
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union {
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BitField<0x00, 0x5, u32> operand_desc_id;
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BitField<0x07, 0x5, u32> src2;
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BitField<0x0c, 0x7, u32> src1;
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BitField<0x13, 0x7, u32> dest;
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} common;
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// Format used for flow control instructions ("if")
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union {
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BitField<0x00, 0x8, u32> num_instructions;
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BitField<0x0a, 0xc, u32> offset_words;
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} flow_control;
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};
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union SwizzlePattern {
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u32 hex;
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enum class Selector : u32 {
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x = 0,
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y = 1,
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z = 2,
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w = 3
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};
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Selector GetSelectorSrc1(int comp) const {
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Selector selectors[] = {
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src1_selector_0, src1_selector_1, src1_selector_2, src1_selector_3
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};
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return selectors[comp];
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}
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Selector GetSelectorSrc2(int comp) const {
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Selector selectors[] = {
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src2_selector_0, src2_selector_1, src2_selector_2, src2_selector_3
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};
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return selectors[comp];
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}
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bool DestComponentEnabled(int i) const {
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return (dest_mask & (0x8 >> i));
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}
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std::string SelectorToString(bool src2) const {
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std::map<Selector, std::string> map = {
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{ Selector::x, "x" },
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{ Selector::y, "y" },
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{ Selector::z, "z" },
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{ Selector::w, "w" }
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};
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std::string ret;
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for (int i = 0; i < 4; ++i) {
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ret += map.at(src2 ? GetSelectorSrc2(i) : GetSelectorSrc1(i));
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}
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return ret;
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}
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std::string DestMaskToString() const {
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std::string ret;
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for (int i = 0; i < 4; ++i) {
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if (!DestComponentEnabled(i))
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ret += "_";
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else
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ret += "xyzw"[i];
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}
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return ret;
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}
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// Components of "dest" that should be written to: LSB=dest.w, MSB=dest.x
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BitField< 0, 4, u32> dest_mask;
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BitField< 5, 2, Selector> src1_selector_3;
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BitField< 7, 2, Selector> src1_selector_2;
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BitField< 9, 2, Selector> src1_selector_1;
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BitField<11, 2, Selector> src1_selector_0;
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BitField<14, 2, Selector> src2_selector_3;
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BitField<16, 2, Selector> src2_selector_2;
|
||||
BitField<18, 2, Selector> src2_selector_1;
|
||||
BitField<20, 2, Selector> src2_selector_0;
|
||||
|
||||
BitField<31, 1, u32> flag; // not sure what this means, maybe it's the sign?
|
||||
};
|
||||
|
||||
void SubmitShaderMemoryChange(u32 addr, u32 value);
|
||||
void SubmitSwizzleDataChange(u32 addr, u32 value);
|
||||
|
||||
OutputVertex RunShader(const InputVertex& input, int num_attributes);
|
||||
|
||||
Math::Vec4<float24>& GetFloatUniform(u32 index);
|
||||
|
||||
} // namespace
|
||||
|
||||
} // namespace
|
||||
|
||||
Loading…
Reference in New Issue