shader/memory_util: Deduplicate code
Deduplicate code shared between vk_pipeline_cache and gl_shader_cache as well as shader decoder code. While we are at it, fix a bug in gl_shader_cache where compute shaders had an start offset of a stage shader.master
ReinUsesLisp
parent
26f2820ae3
commit
ddd82ef42b
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// Copyright 2020 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <cstddef>
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#include <boost/container_hash/hash.hpp>
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#include "common/common_types.h"
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#include "core/core.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/memory_manager.h"
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#include "video_core/shader/memory_util.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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GPUVAddr GetShaderAddress(Core::System& system,
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Tegra::Engines::Maxwell3D::Regs::ShaderProgram program) {
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const auto& gpu{system.GPU().Maxwell3D()};
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const auto& shader_config{gpu.regs.shader_config[static_cast<std::size_t>(program)]};
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return gpu.regs.code_address.CodeAddress() + shader_config.offset;
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}
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bool IsSchedInstruction(std::size_t offset, std::size_t main_offset) {
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// Sched instructions appear once every 4 instructions.
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constexpr std::size_t SchedPeriod = 4;
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const std::size_t absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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std::size_t CalculateProgramSize(const ProgramCode& program, bool is_compute) {
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// This is the encoded version of BRA that jumps to itself. All Nvidia
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// shaders end with one.
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static constexpr u64 SELF_JUMPING_BRANCH = 0xE2400FFFFF07000FULL;
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static constexpr u64 MASK = 0xFFFFFFFFFF7FFFFFULL;
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const std::size_t start_offset = is_compute ? KERNEL_MAIN_OFFSET : STAGE_MAIN_OFFSET;
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std::size_t offset = start_offset;
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while (offset < program.size()) {
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const u64 instruction = program[offset];
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if (!IsSchedInstruction(offset, start_offset)) {
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if ((instruction & MASK) == SELF_JUMPING_BRANCH) {
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// End on Maxwell's "nop" instruction
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break;
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}
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if (instruction == 0) {
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break;
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}
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}
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++offset;
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}
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// The last instruction is included in the program size
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return std::min(offset + 1, program.size());
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}
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ProgramCode GetShaderCode(Tegra::MemoryManager& memory_manager, GPUVAddr gpu_addr,
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const u8* host_ptr, bool is_compute) {
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ProgramCode code(VideoCommon::Shader::MAX_PROGRAM_LENGTH);
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ASSERT_OR_EXECUTE(host_ptr != nullptr, { return code; });
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memory_manager.ReadBlockUnsafe(gpu_addr, code.data(), code.size() * sizeof(u64));
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code.resize(CalculateProgramSize(code, is_compute));
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return code;
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}
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u64 GetUniqueIdentifier(Tegra::Engines::ShaderType shader_type, bool is_a, const ProgramCode& code,
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const ProgramCode& code_b) {
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u64 unique_identifier = boost::hash_value(code);
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if (is_a) {
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// VertexA programs include two programs
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boost::hash_combine(unique_identifier, boost::hash_value(code_b));
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}
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return unique_identifier;
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}
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} // namespace VideoCommon::Shader
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@ -0,0 +1,47 @@
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// Copyright 2020 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <cstddef>
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#include <vector>
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#include "common/common_types.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/shader_type.h"
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namespace Core {
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class System;
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}
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namespace Tegra {
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class MemoryManager;
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}
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namespace VideoCommon::Shader {
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using ProgramCode = std::vector<u64>;
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constexpr u32 STAGE_MAIN_OFFSET = 10;
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constexpr u32 KERNEL_MAIN_OFFSET = 0;
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/// Gets the address for the specified shader stage program
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GPUVAddr GetShaderAddress(Core::System& system,
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Tegra::Engines::Maxwell3D::Regs::ShaderProgram program);
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/// Gets if the current instruction offset is a scheduler instruction
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bool IsSchedInstruction(std::size_t offset, std::size_t main_offset);
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/// Calculates the size of a program stream
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std::size_t CalculateProgramSize(const ProgramCode& program, bool is_compute);
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/// Gets the shader program code from memory for the specified address
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ProgramCode GetShaderCode(Tegra::MemoryManager& memory_manager, GPUVAddr gpu_addr,
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const u8* host_ptr, bool is_compute);
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/// Hashes one (or two) program streams
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u64 GetUniqueIdentifier(Tegra::Engines::ShaderType shader_type, bool is_a, const ProgramCode& code,
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const ProgramCode& code_b = {});
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} // namespace VideoCommon::Shader
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