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@ -7,6 +7,7 @@
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#include <string>
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#include <string_view>
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#include <boost/optional.hpp>
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#include <fmt/format.h>
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#include "common/assert.h"
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@ -29,11 +30,32 @@ using Tegra::Shader::SubOp;
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constexpr u32 PROGRAM_END = MAX_PROGRAM_CODE_LENGTH;
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constexpr u32 PROGRAM_HEADER_SIZE = sizeof(Tegra::Shader::Header);
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enum : u32 { POSITION_VARYING_LOCATION = 0, GENERIC_VARYING_START_LOCATION = 1 };
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constexpr u32 MAX_GEOMETRY_BUFFERS = 6;
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constexpr u32 MAX_ATTRIBUTES = 0x100; // Size in vec4s, this value is untested
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class DecompileFail : public std::runtime_error {
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public:
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using std::runtime_error::runtime_error;
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};
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/// Translate topology
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static std::string GetTopologyName(Tegra::Shader::OutputTopology topology) {
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switch (topology) {
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case Tegra::Shader::OutputTopology::PointList:
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return "points";
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case Tegra::Shader::OutputTopology::LineStrip:
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return "line_strip";
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case Tegra::Shader::OutputTopology::TriangleStrip:
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return "triangle_strip";
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default:
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LOG_CRITICAL(Render_OpenGL, "Unknown output topology {}", static_cast<u32>(topology));
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UNREACHABLE();
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return "points";
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}
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}
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/// Describes the behaviour of code path of a given entry point and a return point.
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enum class ExitMethod {
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Undetermined, ///< Internal value. Only occur when analyzing JMP loop.
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@ -253,8 +275,9 @@ enum class InternalFlag : u64 {
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class GLSLRegisterManager {
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public:
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GLSLRegisterManager(ShaderWriter& shader, ShaderWriter& declarations,
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const Maxwell3D::Regs::ShaderStage& stage, const std::string& suffix)
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: shader{shader}, declarations{declarations}, stage{stage}, suffix{suffix} {
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const Maxwell3D::Regs::ShaderStage& stage, const std::string& suffix,
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const Tegra::Shader::Header& header)
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: shader{shader}, declarations{declarations}, stage{stage}, suffix{suffix}, header{header} {
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BuildRegisterList();
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BuildInputList();
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}
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@ -358,11 +381,13 @@ public:
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* @param reg The destination register to use.
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* @param elem The element to use for the operation.
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* @param attribute The input attribute to use as the source value.
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* @param vertex The register that decides which vertex to read from (used in GS).
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*/
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void SetRegisterToInputAttibute(const Register& reg, u64 elem, Attribute::Index attribute,
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const Tegra::Shader::IpaMode& input_mode) {
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const Tegra::Shader::IpaMode& input_mode,
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boost::optional<Register> vertex = {}) {
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const std::string dest = GetRegisterAsFloat(reg);
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const std::string src = GetInputAttribute(attribute, input_mode) + GetSwizzle(elem);
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const std::string src = GetInputAttribute(attribute, input_mode, vertex) + GetSwizzle(elem);
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shader.AddLine(dest + " = " + src + ';');
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}
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@ -391,16 +416,29 @@ public:
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* are stored as floats, so this may require conversion.
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* @param attribute The destination output attribute.
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* @param elem The element to use for the operation.
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* @param reg The register to use as the source value.
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* @param val_reg The register to use as the source value.
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* @param buf_reg The register that tells which buffer to write to (used in geometry shaders).
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*/
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void SetOutputAttributeToRegister(Attribute::Index attribute, u64 elem, const Register& reg) {
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void SetOutputAttributeToRegister(Attribute::Index attribute, u64 elem, const Register& val_reg,
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const Register& buf_reg) {
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const std::string dest = GetOutputAttribute(attribute);
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const std::string src = GetRegisterAsFloat(reg);
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const std::string src = GetRegisterAsFloat(val_reg);
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if (!dest.empty()) {
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// Can happen with unknown/unimplemented output attributes, in which case we ignore the
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// instruction for now.
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shader.AddLine(dest + GetSwizzle(elem) + " = " + src + ';');
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if (stage == Maxwell3D::Regs::ShaderStage::Geometry) {
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// TODO(Rodrigo): nouveau sets some attributes after setting emitting a geometry
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// shader. These instructions use a dirty register as buffer index. To avoid some
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// drivers from complaining for the out of boundary writes, guard them.
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const std::string buf_index{"min(" + GetRegisterAsInteger(buf_reg) + ", " +
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std::to_string(MAX_GEOMETRY_BUFFERS - 1) + ')'};
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shader.AddLine("amem[" + buf_index + "][" +
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std::to_string(static_cast<u32>(attribute)) + ']' +
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GetSwizzle(elem) + " = " + src + ';');
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} else {
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shader.AddLine(dest + GetSwizzle(elem) + " = " + src + ';');
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}
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}
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}
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@ -441,58 +479,18 @@ public:
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}
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}
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/// Add declarations for registers
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/// Add declarations.
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void GenerateDeclarations(const std::string& suffix) {
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for (const auto& reg : regs) {
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declarations.AddLine(GLSLRegister::GetTypeString() + ' ' + reg.GetPrefixString() +
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std::to_string(reg.GetIndex()) + '_' + suffix + " = 0;");
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}
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declarations.AddNewLine();
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for (u32 ii = 0; ii < static_cast<u64>(InternalFlag::Amount); ii++) {
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const InternalFlag code = static_cast<InternalFlag>(ii);
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declarations.AddLine("bool " + GetInternalFlag(code) + " = false;");
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}
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declarations.AddNewLine();
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for (const auto element : declr_input_attribute) {
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// TODO(bunnei): Use proper number of elements for these
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u32 idx =
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static_cast<u32>(element.first) - static_cast<u32>(Attribute::Index::Attribute_0);
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declarations.AddLine("layout(location = " + std::to_string(idx) + ")" +
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GetInputFlags(element.first) + "in vec4 " +
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GetInputAttribute(element.first, element.second) + ';');
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}
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declarations.AddNewLine();
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for (const auto& index : declr_output_attribute) {
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// TODO(bunnei): Use proper number of elements for these
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declarations.AddLine("layout(location = " +
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std::to_string(static_cast<u32>(index) -
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static_cast<u32>(Attribute::Index::Attribute_0)) +
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") out vec4 " + GetOutputAttribute(index) + ';');
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}
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declarations.AddNewLine();
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for (const auto& entry : GetConstBuffersDeclarations()) {
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declarations.AddLine("layout(std140) uniform " + entry.GetName());
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declarations.AddLine('{');
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declarations.AddLine(" vec4 c" + std::to_string(entry.GetIndex()) +
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"[MAX_CONSTBUFFER_ELEMENTS];");
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declarations.AddLine("};");
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declarations.AddNewLine();
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}
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declarations.AddNewLine();
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const auto& samplers = GetSamplers();
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for (const auto& sampler : samplers) {
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declarations.AddLine("uniform " + sampler.GetTypeString() + ' ' + sampler.GetName() +
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';');
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}
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declarations.AddNewLine();
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GenerateRegisters(suffix);
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GenerateInternalFlags();
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GenerateInputAttrs();
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GenerateOutputAttrs();
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GenerateConstBuffers();
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GenerateSamplers();
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GenerateGeometry();
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}
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/// Returns a list of constant buffer declarations
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/// Returns a list of constant buffer declarations.
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std::vector<ConstBufferEntry> GetConstBuffersDeclarations() const {
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std::vector<ConstBufferEntry> result;
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std::copy_if(declr_const_buffers.begin(), declr_const_buffers.end(),
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@ -500,7 +498,7 @@ public:
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return result;
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}
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/// Returns a list of samplers used in the shader
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/// Returns a list of samplers used in the shader.
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const std::vector<SamplerEntry>& GetSamplers() const {
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return used_samplers;
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}
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@ -509,7 +507,7 @@ public:
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/// necessary.
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std::string AccessSampler(const Sampler& sampler, Tegra::Shader::TextureType type,
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bool is_array, bool is_shadow) {
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const std::size_t offset = static_cast<std::size_t>(sampler.index.Value());
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const auto offset = static_cast<std::size_t>(sampler.index.Value());
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// If this sampler has already been used, return the existing mapping.
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const auto itr =
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@ -530,6 +528,129 @@ public:
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}
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private:
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/// Generates declarations for registers.
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void GenerateRegisters(const std::string& suffix) {
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for (const auto& reg : regs) {
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declarations.AddLine(GLSLRegister::GetTypeString() + ' ' + reg.GetPrefixString() +
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std::to_string(reg.GetIndex()) + '_' + suffix + " = 0;");
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}
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declarations.AddNewLine();
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}
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/// Generates declarations for internal flags.
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void GenerateInternalFlags() {
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for (u32 ii = 0; ii < static_cast<u64>(InternalFlag::Amount); ii++) {
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const InternalFlag code = static_cast<InternalFlag>(ii);
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declarations.AddLine("bool " + GetInternalFlag(code) + " = false;");
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}
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declarations.AddNewLine();
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}
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/// Generates declarations for input attributes.
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void GenerateInputAttrs() {
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if (stage != Maxwell3D::Regs::ShaderStage::Vertex) {
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const std::string attr =
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stage == Maxwell3D::Regs::ShaderStage::Geometry ? "gs_position[]" : "position";
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declarations.AddLine("layout (location = " + std::to_string(POSITION_VARYING_LOCATION) +
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") in vec4 " + attr + ';');
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}
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for (const auto element : declr_input_attribute) {
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// TODO(bunnei): Use proper number of elements for these
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u32 idx =
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static_cast<u32>(element.first) - static_cast<u32>(Attribute::Index::Attribute_0);
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if (stage != Maxwell3D::Regs::ShaderStage::Vertex) {
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// If inputs are varyings, add an offset
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idx += GENERIC_VARYING_START_LOCATION;
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}
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std::string attr{GetInputAttribute(element.first, element.second)};
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if (stage == Maxwell3D::Regs::ShaderStage::Geometry) {
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attr = "gs_" + attr + "[]";
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}
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declarations.AddLine("layout (location = " + std::to_string(idx) + ") " +
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GetInputFlags(element.first) + "in vec4 " + attr + ';');
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}
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declarations.AddNewLine();
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}
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/// Generates declarations for output attributes.
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void GenerateOutputAttrs() {
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if (stage != Maxwell3D::Regs::ShaderStage::Fragment) {
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declarations.AddLine("layout (location = " + std::to_string(POSITION_VARYING_LOCATION) +
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") out vec4 position;");
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}
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for (const auto& index : declr_output_attribute) {
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// TODO(bunnei): Use proper number of elements for these
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const u32 idx = static_cast<u32>(index) -
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static_cast<u32>(Attribute::Index::Attribute_0) +
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GENERIC_VARYING_START_LOCATION;
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declarations.AddLine("layout (location = " + std::to_string(idx) + ") out vec4 " +
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GetOutputAttribute(index) + ';');
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}
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declarations.AddNewLine();
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}
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/// Generates declarations for constant buffers.
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void GenerateConstBuffers() {
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for (const auto& entry : GetConstBuffersDeclarations()) {
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declarations.AddLine("layout (std140) uniform " + entry.GetName());
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declarations.AddLine('{');
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declarations.AddLine(" vec4 c" + std::to_string(entry.GetIndex()) +
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"[MAX_CONSTBUFFER_ELEMENTS];");
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declarations.AddLine("};");
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declarations.AddNewLine();
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}
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declarations.AddNewLine();
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}
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/// Generates declarations for samplers.
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void GenerateSamplers() {
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const auto& samplers = GetSamplers();
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for (const auto& sampler : samplers) {
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declarations.AddLine("uniform " + sampler.GetTypeString() + ' ' + sampler.GetName() +
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';');
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}
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declarations.AddNewLine();
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}
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/// Generates declarations used for geometry shaders.
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void GenerateGeometry() {
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if (stage != Maxwell3D::Regs::ShaderStage::Geometry)
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return;
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declarations.AddLine(
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"layout (" + GetTopologyName(header.common3.output_topology) +
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", max_vertices = " + std::to_string(header.common4.max_output_vertices) + ") out;");
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declarations.AddNewLine();
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declarations.AddLine("vec4 amem[" + std::to_string(MAX_GEOMETRY_BUFFERS) + "][" +
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std::to_string(MAX_ATTRIBUTES) + "];");
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declarations.AddNewLine();
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constexpr char buffer[] = "amem[output_buffer]";
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declarations.AddLine("void emit_vertex(uint output_buffer) {");
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++declarations.scope;
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for (const auto element : declr_output_attribute) {
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declarations.AddLine(GetOutputAttribute(element) + " = " + buffer + '[' +
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|
std::to_string(static_cast<u32>(element)) + "];");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
declarations.AddLine("position = " + std::string(buffer) + '[' +
|
|
|
|
|
std::to_string(static_cast<u32>(Attribute::Index::Position)) + "];");
|
|
|
|
|
|
|
|
|
|
// If a geometry shader is attached, it will always flip (it's the last stage before
|
|
|
|
|
// fragment). For more info about flipping, refer to gl_shader_gen.cpp.
|
|
|
|
|
declarations.AddLine("position.xy *= viewport_flip.xy;");
|
|
|
|
|
declarations.AddLine("gl_Position = position;");
|
|
|
|
|
declarations.AddLine("position.w = 1.0;");
|
|
|
|
|
declarations.AddLine("EmitVertex();");
|
|
|
|
|
--declarations.scope;
|
|
|
|
|
declarations.AddLine('}');
|
|
|
|
|
declarations.AddNewLine();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// Generates code representing a temporary (GPR) register.
|
|
|
|
|
std::string GetRegister(const Register& reg, unsigned elem) {
|
|
|
|
|
if (reg == Register::ZeroIndex) {
|
|
|
|
|
@ -586,11 +707,19 @@ private:
|
|
|
|
|
|
|
|
|
|
/// Generates code representing an input attribute register.
|
|
|
|
|
std::string GetInputAttribute(Attribute::Index attribute,
|
|
|
|
|
const Tegra::Shader::IpaMode& input_mode) {
|
|
|
|
|
const Tegra::Shader::IpaMode& input_mode,
|
|
|
|
|
boost::optional<Register> vertex = {}) {
|
|
|
|
|
auto GeometryPass = [&](const std::string& name) {
|
|
|
|
|
if (stage == Maxwell3D::Regs::ShaderStage::Geometry && vertex) {
|
|
|
|
|
return "gs_" + name + '[' + GetRegisterAsInteger(vertex.value(), 0, false) + ']';
|
|
|
|
|
}
|
|
|
|
|
return name;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
switch (attribute) {
|
|
|
|
|
case Attribute::Index::Position:
|
|
|
|
|
if (stage != Maxwell3D::Regs::ShaderStage::Fragment) {
|
|
|
|
|
return "position";
|
|
|
|
|
return GeometryPass("position");
|
|
|
|
|
} else {
|
|
|
|
|
return "vec4(gl_FragCoord.x, gl_FragCoord.y, gl_FragCoord.z, 1.0)";
|
|
|
|
|
}
|
|
|
|
|
@ -619,7 +748,7 @@ private:
|
|
|
|
|
UNREACHABLE();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return "input_attribute_" + std::to_string(index);
|
|
|
|
|
return GeometryPass("input_attribute_" + std::to_string(index));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unhandled input attribute: {}", static_cast<u32>(attribute));
|
|
|
|
|
@ -672,7 +801,7 @@ private:
|
|
|
|
|
return out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/// Generates code representing an output attribute register.
|
|
|
|
|
/// Generates code representing the declaration name of an output attribute register.
|
|
|
|
|
std::string GetOutputAttribute(Attribute::Index attribute) {
|
|
|
|
|
switch (attribute) {
|
|
|
|
|
case Attribute::Index::Position:
|
|
|
|
|
@ -708,6 +837,7 @@ private:
|
|
|
|
|
std::vector<SamplerEntry> used_samplers;
|
|
|
|
|
const Maxwell3D::Regs::ShaderStage& stage;
|
|
|
|
|
const std::string& suffix;
|
|
|
|
|
const Tegra::Shader::Header& header;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
class GLSLGenerator {
|
|
|
|
|
@ -1103,8 +1233,8 @@ private:
|
|
|
|
|
return offset + 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
shader.AddLine("// " + std::to_string(offset) + ": " + opcode->GetName() + " (" +
|
|
|
|
|
std::to_string(instr.value) + ')');
|
|
|
|
|
shader.AddLine(
|
|
|
|
|
fmt::format("// {}: {} (0x{:016x})", offset, opcode->GetName(), instr.value));
|
|
|
|
|
|
|
|
|
|
using Tegra::Shader::Pred;
|
|
|
|
|
ASSERT_MSG(instr.pred.full_pred != Pred::NeverExecute,
|
|
|
|
|
@ -1826,7 +1956,7 @@ private:
|
|
|
|
|
const auto LoadNextElement = [&](u32 reg_offset) {
|
|
|
|
|
regs.SetRegisterToInputAttibute(instr.gpr0.Value() + reg_offset, next_element,
|
|
|
|
|
static_cast<Attribute::Index>(next_index),
|
|
|
|
|
input_mode);
|
|
|
|
|
input_mode, instr.gpr39.Value());
|
|
|
|
|
|
|
|
|
|
// Load the next attribute element into the following register. If the element
|
|
|
|
|
// to load goes beyond the vec4 size, load the first element of the next
|
|
|
|
|
@ -1890,8 +2020,8 @@ private:
|
|
|
|
|
|
|
|
|
|
const auto StoreNextElement = [&](u32 reg_offset) {
|
|
|
|
|
regs.SetOutputAttributeToRegister(static_cast<Attribute::Index>(next_index),
|
|
|
|
|
next_element,
|
|
|
|
|
instr.gpr0.Value() + reg_offset);
|
|
|
|
|
next_element, instr.gpr0.Value() + reg_offset,
|
|
|
|
|
instr.gpr39.Value());
|
|
|
|
|
|
|
|
|
|
// Load the next attribute element into the following register. If the element
|
|
|
|
|
// to load goes beyond the vec4 size, load the first element of the next
|
|
|
|
|
@ -2734,6 +2864,52 @@ private:
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case OpCode::Id::OUT_R: {
|
|
|
|
|
ASSERT(instr.gpr20.Value() == Register::ZeroIndex);
|
|
|
|
|
ASSERT_MSG(stage == Maxwell3D::Regs::ShaderStage::Geometry,
|
|
|
|
|
"OUT is expected to be used in a geometry shader.");
|
|
|
|
|
|
|
|
|
|
if (instr.out.emit) {
|
|
|
|
|
// gpr0 is used to store the next address. Hardware returns a pointer but
|
|
|
|
|
// we just return the next index with a cyclic cap.
|
|
|
|
|
const std::string current{regs.GetRegisterAsInteger(instr.gpr8, 0, false)};
|
|
|
|
|
const std::string next = "((" + current + " + 1" + ") % " +
|
|
|
|
|
std::to_string(MAX_GEOMETRY_BUFFERS) + ')';
|
|
|
|
|
shader.AddLine("emit_vertex(" + current + ");");
|
|
|
|
|
regs.SetRegisterToInteger(instr.gpr0, false, 0, next, 1, 1);
|
|
|
|
|
}
|
|
|
|
|
if (instr.out.cut) {
|
|
|
|
|
shader.AddLine("EndPrimitive();");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case OpCode::Id::MOV_SYS: {
|
|
|
|
|
switch (instr.sys20) {
|
|
|
|
|
case Tegra::Shader::SystemVariable::InvocationInfo: {
|
|
|
|
|
LOG_WARNING(HW_GPU, "MOV_SYS instruction with InvocationInfo is incomplete");
|
|
|
|
|
regs.SetRegisterToInteger(instr.gpr0, false, 0, "0u", 1, 1);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
default: {
|
|
|
|
|
LOG_CRITICAL(HW_GPU, "Unhandled system move: {}",
|
|
|
|
|
static_cast<u32>(instr.sys20.Value()));
|
|
|
|
|
UNREACHABLE();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case OpCode::Id::ISBERD: {
|
|
|
|
|
ASSERT(instr.isberd.o == 0);
|
|
|
|
|
ASSERT(instr.isberd.skew == 0);
|
|
|
|
|
ASSERT(instr.isberd.shift == Tegra::Shader::IsberdShift::None);
|
|
|
|
|
ASSERT(instr.isberd.mode == Tegra::Shader::IsberdMode::None);
|
|
|
|
|
ASSERT_MSG(stage == Maxwell3D::Regs::ShaderStage::Geometry,
|
|
|
|
|
"ISBERD is expected to be used in a geometry shader.");
|
|
|
|
|
LOG_WARNING(HW_GPU, "ISBERD instruction is incomplete");
|
|
|
|
|
regs.SetRegisterToFloat(instr.gpr0, 0, regs.GetRegisterAsFloat(instr.gpr8), 1, 1);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case OpCode::Id::BRA: {
|
|
|
|
|
ASSERT_MSG(instr.bra.constant_buffer == 0,
|
|
|
|
|
"BRA with constant buffers are not implemented");
|
|
|
|
|
@ -2907,7 +3083,7 @@ private:
|
|
|
|
|
|
|
|
|
|
ShaderWriter shader;
|
|
|
|
|
ShaderWriter declarations;
|
|
|
|
|
GLSLRegisterManager regs{shader, declarations, stage, suffix};
|
|
|
|
|
GLSLRegisterManager regs{shader, declarations, stage, suffix, header};
|
|
|
|
|
|
|
|
|
|
// Declarations
|
|
|
|
|
std::set<std::string> declr_predicates;
|
|
|
|
|
|
bunnei
GitHub