GPU: Delay Fences.

merge-requests/60/head
Fernando Sahmkow 2020-02-16 16:24:37 +07:00
parent 8b1eb44b3e
commit 339d0d9d6c
6 changed files with 20 additions and 2 deletions

@ -34,6 +34,7 @@ void DmaPusher::DispatchCalls() {
} }
gpu.FlushCommands(); gpu.FlushCommands();
gpu.SyncGuestHost(); gpu.SyncGuestHost();
gpu.OnCommandListEnd();
} }
bool DmaPusher::Step() { bool DmaPusher::Step() {

@ -397,6 +397,14 @@ void Maxwell3D::StampQueryResult(u64 payload, bool long_query) {
} }
} }
void Maxwell3D::ReleaseFences() {
for (const auto pair : delay_fences) {
const auto [addr, payload] = pair;
memory_manager.Write<u32>(addr, static_cast<u32>(payload));
}
delay_fences.clear();
}
void Maxwell3D::ProcessQueryGet() { void Maxwell3D::ProcessQueryGet() {
// TODO(Subv): Support the other query units. // TODO(Subv): Support the other query units.
ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop, ASSERT_MSG(regs.query.query_get.unit == Regs::QueryUnit::Crop,
@ -407,7 +415,7 @@ void Maxwell3D::ProcessQueryGet() {
rasterizer.FlushCommands(); rasterizer.FlushCommands();
rasterizer.SyncGuestHost(); rasterizer.SyncGuestHost();
const u64 result = regs.query.query_sequence; const u64 result = regs.query.query_sequence;
StampQueryResult(result, regs.query.query_get.short_query == 0); delay_fences.emplace_back(regs.query.QueryAddress(), result);
break; break;
} }
case Regs::QueryOperation::Acquire: case Regs::QueryOperation::Acquire:

@ -1427,6 +1427,8 @@ public:
Tables tables{}; Tables tables{};
} dirty; } dirty;
void ReleaseFences();
private: private:
void InitializeRegisterDefaults(); void InitializeRegisterDefaults();
@ -1467,6 +1469,8 @@ private:
std::array<u8, Regs::NUM_REGS> dirty_pointers{}; std::array<u8, Regs::NUM_REGS> dirty_pointers{};
std::vector<std::pair<GPUVAddr, u64>> delay_fences;
/// Retrieves information about a specific TIC entry from the TIC buffer. /// Retrieves information about a specific TIC entry from the TIC buffer.
Texture::TICEntry GetTICEntry(u32 tic_index) const; Texture::TICEntry GetTICEntry(u32 tic_index) const;

@ -145,6 +145,10 @@ void GPU::FlushCommands() {
void GPU::SyncGuestHost() { void GPU::SyncGuestHost() {
renderer->Rasterizer().SyncGuestHost(); renderer->Rasterizer().SyncGuestHost();
} }
void GPU::OnCommandListEnd() {
maxwell_3d->ReleaseFences();
}
// Note that, traditionally, methods are treated as 4-byte addressable locations, and hence // Note that, traditionally, methods are treated as 4-byte addressable locations, and hence
// their numbers are written down multiplied by 4 in Docs. Here we are not multiply by 4. // their numbers are written down multiplied by 4 in Docs. Here we are not multiply by 4.
// So the values you see in docs might be multiplied by 4. // So the values you see in docs might be multiplied by 4.

@ -157,6 +157,7 @@ public:
void FlushCommands(); void FlushCommands();
void SyncGuestHost(); void SyncGuestHost();
void OnCommandListEnd();
/// Returns a reference to the Maxwell3D GPU engine. /// Returns a reference to the Maxwell3D GPU engine.
Engines::Maxwell3D& Maxwell3D(); Engines::Maxwell3D& Maxwell3D();

@ -78,7 +78,7 @@ void ThreadManager::SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
} }
void ThreadManager::FlushRegion(VAddr addr, u64 size) { void ThreadManager::FlushRegion(VAddr addr, u64 size) {
system.Renderer().Rasterizer().FlushRegion(addr, size); PushCommand(FlushRegionCommand(addr, size));
} }
void ThreadManager::InvalidateRegion(VAddr addr, u64 size) { void ThreadManager::InvalidateRegion(VAddr addr, u64 size) {