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@ -215,15 +215,14 @@ ConfigureFuncPtr ConfigureFunc(const std::array<vk::ShaderModule, NUM_STAGES>& m
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} // Anonymous namespace
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} // Anonymous namespace
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GraphicsPipeline::GraphicsPipeline(
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GraphicsPipeline::GraphicsPipeline(
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Tegra::Engines::Maxwell3D& maxwell3d_, Tegra::MemoryManager& gpu_memory_, Scheduler& scheduler_,
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Scheduler& scheduler_, BufferCache& buffer_cache_, TextureCache& texture_cache_,
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BufferCache& buffer_cache_, TextureCache& texture_cache_,
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VideoCore::ShaderNotify* shader_notify, const Device& device_, DescriptorPool& descriptor_pool,
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VideoCore::ShaderNotify* shader_notify, const Device& device_, DescriptorPool& descriptor_pool,
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UpdateDescriptorQueue& update_descriptor_queue_, Common::ThreadWorker* worker_thread,
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UpdateDescriptorQueue& update_descriptor_queue_, Common::ThreadWorker* worker_thread,
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PipelineStatistics* pipeline_statistics, RenderPassCache& render_pass_cache,
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PipelineStatistics* pipeline_statistics, RenderPassCache& render_pass_cache,
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const GraphicsPipelineCacheKey& key_, std::array<vk::ShaderModule, NUM_STAGES> stages,
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const GraphicsPipelineCacheKey& key_, std::array<vk::ShaderModule, NUM_STAGES> stages,
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const std::array<const Shader::Info*, NUM_STAGES>& infos)
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const std::array<const Shader::Info*, NUM_STAGES>& infos)
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: key{key_}, maxwell3d{maxwell3d_}, gpu_memory{gpu_memory_}, device{device_},
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: key{key_}, device{device_}, texture_cache{texture_cache_},
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texture_cache{texture_cache_}, buffer_cache{buffer_cache_}, scheduler{scheduler_},
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buffer_cache{buffer_cache_}, scheduler{scheduler_},
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update_descriptor_queue{update_descriptor_queue_}, spv_modules{std::move(stages)} {
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update_descriptor_queue{update_descriptor_queue_}, spv_modules{std::move(stages)} {
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if (shader_notify) {
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if (shader_notify) {
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shader_notify->MarkShaderBuilding();
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shader_notify->MarkShaderBuilding();
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@ -288,7 +287,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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buffer_cache.SetUniformBuffersState(enabled_uniform_buffer_masks, &uniform_buffer_sizes);
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buffer_cache.SetUniformBuffersState(enabled_uniform_buffer_masks, &uniform_buffer_sizes);
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const auto& regs{maxwell3d.regs};
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const auto& regs{maxwell3d->regs};
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const bool via_header_index{regs.sampler_index == Maxwell::SamplerIndex::ViaHeaderIndex};
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const bool via_header_index{regs.sampler_index == Maxwell::SamplerIndex::ViaHeaderIndex};
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const auto config_stage{[&](size_t stage) LAMBDA_FORCEINLINE {
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const auto config_stage{[&](size_t stage) LAMBDA_FORCEINLINE {
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const Shader::Info& info{stage_infos[stage]};
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const Shader::Info& info{stage_infos[stage]};
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@ -302,7 +301,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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++ssbo_index;
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++ssbo_index;
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}
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}
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}
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}
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const auto& cbufs{maxwell3d.state.shader_stages[stage].const_buffers};
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const auto& cbufs{maxwell3d->state.shader_stages[stage].const_buffers};
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const auto read_handle{[&](const auto& desc, u32 index) {
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const auto read_handle{[&](const auto& desc, u32 index) {
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ASSERT(cbufs[desc.cbuf_index].enabled);
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ASSERT(cbufs[desc.cbuf_index].enabled);
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const u32 index_offset{index << desc.size_shift};
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const u32 index_offset{index << desc.size_shift};
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@ -315,13 +314,13 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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const u32 second_offset{desc.secondary_cbuf_offset + index_offset};
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const u32 second_offset{desc.secondary_cbuf_offset + index_offset};
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const GPUVAddr separate_addr{cbufs[desc.secondary_cbuf_index].address +
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const GPUVAddr separate_addr{cbufs[desc.secondary_cbuf_index].address +
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second_offset};
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second_offset};
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const u32 lhs_raw{gpu_memory.Read<u32>(addr)};
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const u32 lhs_raw{gpu_memory->Read<u32>(addr)};
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const u32 rhs_raw{gpu_memory.Read<u32>(separate_addr)};
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const u32 rhs_raw{gpu_memory->Read<u32>(separate_addr)};
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const u32 raw{lhs_raw | rhs_raw};
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const u32 raw{lhs_raw | rhs_raw};
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return TexturePair(raw, via_header_index);
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return TexturePair(raw, via_header_index);
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}
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}
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}
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}
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return TexturePair(gpu_memory.Read<u32>(addr), via_header_index);
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return TexturePair(gpu_memory->Read<u32>(addr), via_header_index);
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}};
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}};
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const auto add_image{[&](const auto& desc, bool blacklist) LAMBDA_FORCEINLINE {
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const auto add_image{[&](const auto& desc, bool blacklist) LAMBDA_FORCEINLINE {
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for (u32 index = 0; index < desc.count; ++index) {
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for (u32 index = 0; index < desc.count; ++index) {
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