mirror of https://git.suyu.dev/suyu/suyu
VideoCore: Split geometry pipeline regs from Regs struct
Yuri Kunde Schlesner
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// Copyright 2017 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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namespace Pica {
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struct PipelineRegs {
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enum class VertexAttributeFormat : u64 {
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BYTE = 0,
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UBYTE = 1,
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SHORT = 2,
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FLOAT = 3,
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};
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struct {
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BitField<0, 29, u32> base_address;
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PAddr GetPhysicalBaseAddress() const {
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return base_address * 8;
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}
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// Descriptor for internal vertex attributes
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union {
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BitField<0, 2, VertexAttributeFormat> format0; // size of one element
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BitField<2, 2, u64> size0; // number of elements minus 1
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BitField<4, 2, VertexAttributeFormat> format1;
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BitField<6, 2, u64> size1;
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BitField<8, 2, VertexAttributeFormat> format2;
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BitField<10, 2, u64> size2;
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BitField<12, 2, VertexAttributeFormat> format3;
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BitField<14, 2, u64> size3;
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BitField<16, 2, VertexAttributeFormat> format4;
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BitField<18, 2, u64> size4;
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BitField<20, 2, VertexAttributeFormat> format5;
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BitField<22, 2, u64> size5;
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BitField<24, 2, VertexAttributeFormat> format6;
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BitField<26, 2, u64> size6;
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BitField<28, 2, VertexAttributeFormat> format7;
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BitField<30, 2, u64> size7;
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BitField<32, 2, VertexAttributeFormat> format8;
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BitField<34, 2, u64> size8;
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BitField<36, 2, VertexAttributeFormat> format9;
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BitField<38, 2, u64> size9;
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BitField<40, 2, VertexAttributeFormat> format10;
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BitField<42, 2, u64> size10;
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BitField<44, 2, VertexAttributeFormat> format11;
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BitField<46, 2, u64> size11;
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BitField<48, 12, u64> attribute_mask;
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// number of total attributes minus 1
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BitField<60, 4, u64> max_attribute_index;
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};
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inline VertexAttributeFormat GetFormat(int n) const {
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VertexAttributeFormat formats[] = {format0, format1, format2, format3,
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format4, format5, format6, format7,
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format8, format9, format10, format11};
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return formats[n];
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}
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inline int GetNumElements(int n) const {
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u64 sizes[] = {size0, size1, size2, size3, size4, size5,
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size6, size7, size8, size9, size10, size11};
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return (int)sizes[n] + 1;
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}
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inline int GetElementSizeInBytes(int n) const {
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return (GetFormat(n) == VertexAttributeFormat::FLOAT)
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? 4
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: (GetFormat(n) == VertexAttributeFormat::SHORT) ? 2 : 1;
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}
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inline int GetStride(int n) const {
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return GetNumElements(n) * GetElementSizeInBytes(n);
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}
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inline bool IsDefaultAttribute(int id) const {
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return (id >= 12) || (attribute_mask & (1ULL << id)) != 0;
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}
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inline int GetNumTotalAttributes() const {
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return (int)max_attribute_index + 1;
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}
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// Attribute loaders map the source vertex data to input attributes
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// This e.g. allows to load different attributes from different memory locations
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struct {
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// Source attribute data offset from the base address
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u32 data_offset;
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union {
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BitField<0, 4, u64> comp0;
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BitField<4, 4, u64> comp1;
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BitField<8, 4, u64> comp2;
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BitField<12, 4, u64> comp3;
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BitField<16, 4, u64> comp4;
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BitField<20, 4, u64> comp5;
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BitField<24, 4, u64> comp6;
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BitField<28, 4, u64> comp7;
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BitField<32, 4, u64> comp8;
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BitField<36, 4, u64> comp9;
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BitField<40, 4, u64> comp10;
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BitField<44, 4, u64> comp11;
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// bytes for a single vertex in this loader
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BitField<48, 8, u64> byte_count;
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BitField<60, 4, u64> component_count;
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};
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inline int GetComponent(int n) const {
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u64 components[] = {comp0, comp1, comp2, comp3, comp4, comp5,
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comp6, comp7, comp8, comp9, comp10, comp11};
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return (int)components[n];
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}
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} attribute_loaders[12];
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} vertex_attributes;
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struct {
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enum IndexFormat : u32 {
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BYTE = 0,
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SHORT = 1,
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};
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union {
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BitField<0, 31, u32> offset; // relative to base attribute address
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BitField<31, 1, IndexFormat> format;
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};
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} index_array;
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// Number of vertices to render
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u32 num_vertices;
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INSERT_PADDING_WORDS(0x1);
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// The index of the first vertex to render
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u32 vertex_offset;
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INSERT_PADDING_WORDS(0x3);
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// These two trigger rendering of triangles
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u32 trigger_draw;
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u32 trigger_draw_indexed;
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INSERT_PADDING_WORDS(0x2);
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// These registers are used to setup the default "fall-back" vertex shader attributes
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struct {
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// Index of the current default attribute
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u32 index;
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// Writing to these registers sets the "current" default attribute.
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u32 set_value[3];
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} vs_default_attributes_setup;
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INSERT_PADDING_WORDS(0x2);
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struct {
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// There are two channels that can be used to configure the next command buffer, which can
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// be then executed by writing to the "trigger" registers. There are two reasons why a game
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// might use this feature:
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// 1) With this, an arbitrary number of additional command buffers may be executed in
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// sequence without requiring any intervention of the CPU after the initial one is
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// kicked off.
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// 2) Games can configure these registers to provide a command list subroutine mechanism.
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BitField<0, 20, u32> size[2]; ///< Size (in bytes / 8) of each channel's command buffer
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BitField<0, 28, u32> addr[2]; ///< Physical address / 8 of each channel's command buffer
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u32 trigger[2]; ///< Triggers execution of the channel's command buffer when written to
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unsigned GetSize(unsigned index) const {
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ASSERT(index < 2);
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return 8 * size[index];
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}
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PAddr GetPhysicalAddress(unsigned index) const {
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ASSERT(index < 2);
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return (PAddr)(8 * addr[index]);
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}
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} command_buffer;
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INSERT_PADDING_WORDS(4);
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/// Number of input attributes to the vertex shader minus 1
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BitField<0, 4, u32> max_input_attrib_index;
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INSERT_PADDING_WORDS(2);
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enum class GPUMode : u32 {
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Drawing = 0,
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Configuring = 1,
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};
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GPUMode gpu_mode;
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INSERT_PADDING_WORDS(0x18);
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enum class TriangleTopology : u32 {
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List = 0,
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Strip = 1,
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Fan = 2,
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Shader = 3, // Programmable setup unit implemented in a geometry shader
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};
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BitField<8, 2, TriangleTopology> triangle_topology;
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u32 restart_primitive;
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INSERT_PADDING_WORDS(0x20);
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};
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static_assert(sizeof(PipelineRegs) == 0x80 * sizeof(u32), "PipelineRegs struct has incorrect size");
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} // namespace Pica
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