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Fix thumb ADR instruction alignment

master
mailwl 2016-04-06 14:57:43 +07:00
parent dccadce074
commit 06a4369f75
1 changed files with 2 additions and 6 deletions
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8
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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@ -3955,9 +3955,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
add_inst* const inst_cream = (add_inst*)inst_base->component; add_inst* const inst_cream = (add_inst*)inst_base->component;
u32 rn_val = RN; u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn);
if (inst_cream->Rn == 15)
rn_val += 2 * cpu->GetInstructionSize();
bool carry; bool carry;
bool overflow; bool overflow;
@ -6167,9 +6165,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
sub_inst* const inst_cream = (sub_inst*)inst_base->component; sub_inst* const inst_cream = (sub_inst*)inst_base->component;
u32 rn_val = RN; u32 rn_val = CHECK_READ_REG15_WA(cpu, inst_cream->Rn);
if (inst_cream->Rn == 15)
rn_val += 2 * cpu->GetInstructionSize();
bool carry; bool carry;
bool overflow; bool overflow;