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@ -1049,12 +1049,22 @@ static u32 vfp_single_fadd(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr)
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static u32 vfp_single_fsub(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
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static u32 vfp_single_fsub(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr) {
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LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd);
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LOG_TRACE(Core_ARM11, "s%u = %08x", sn, sd);
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/*
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/*
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* Subtraction is addition with one sign inverted.
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* Subtraction is addition with one sign inverted. Unpack the second operand to perform FTZ if
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* necessary, we can't let fadd do this because a denormal in m might get flushed to +0 in FTZ
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* mode, and the resulting sign of 0 OP +0 differs between fadd and fsub. We do not need to do
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* this for n because +0 OP 0 is always +0 for both fadd and fsub.
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*/
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*/
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struct vfp_single vsm;
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u32 exceptions = vfp_single_unpack(&vsm, m, fpscr);
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if (exceptions & FPSCR_IDC) {
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// The value was flushed to zero, re-pack it.
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m = vfp_single_pack(&vsm);
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}
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if (m != 0x7FC00000) // Only negate if m isn't NaN.
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if (m != 0x7FC00000) // Only negate if m isn't NaN.
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m = vfp_single_packed_negate(m);
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m = vfp_single_packed_negate(m);
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return vfp_single_fadd(state, sd, sn, m, fpscr);
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return vfp_single_fadd(state, sd, sn, m, fpscr) | exceptions;
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}
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}
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/*
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/*
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