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@ -532,7 +532,21 @@ public:
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INSERT_PADDING_WORDS(0x3);
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INSERT_PADDING_WORDS(0x3);
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s32 clear_stencil;
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s32 clear_stencil;
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INSERT_PADDING_WORDS(0x6C);
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INSERT_PADDING_WORDS(0x17);
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struct {
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u32 enable;
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union {
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BitField<0, 16, u32> min_x;
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BitField<16, 16, u32> max_x;
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};
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union {
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BitField<0, 16, u32> min_y;
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BitField<16, 16, u32> max_y;
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};
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} scissor_test;
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INSERT_PADDING_WORDS(0x52);
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s32 stencil_back_func_ref;
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s32 stencil_back_func_ref;
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u32 stencil_back_mask;
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u32 stencil_back_mask;
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@ -1002,6 +1016,7 @@ ASSERT_REG_POSITION(vertex_buffer, 0x35D);
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ASSERT_REG_POSITION(clear_color[0], 0x360);
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ASSERT_REG_POSITION(clear_color[0], 0x360);
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ASSERT_REG_POSITION(clear_depth, 0x364);
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ASSERT_REG_POSITION(clear_depth, 0x364);
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ASSERT_REG_POSITION(clear_stencil, 0x368);
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ASSERT_REG_POSITION(clear_stencil, 0x368);
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ASSERT_REG_POSITION(scissor_test, 0x380);
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ASSERT_REG_POSITION(stencil_back_func_ref, 0x3D5);
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ASSERT_REG_POSITION(stencil_back_func_ref, 0x3D5);
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ASSERT_REG_POSITION(stencil_back_mask, 0x3D6);
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ASSERT_REG_POSITION(stencil_back_mask, 0x3D6);
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ASSERT_REG_POSITION(stencil_back_func_mask, 0x3D7);
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ASSERT_REG_POSITION(stencil_back_func_mask, 0x3D7);
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