Shader: Define a common interface for running vertex shader programs.
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/logging/log.h"
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#include "common/profiler.h"
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#include "video_core/debug_utils/debug_utils.h"
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#include "video_core/pica.h"
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#include "shader.h"
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#include "shader_interpreter.h"
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namespace Pica {
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namespace Shader {
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void Setup(UnitState& state) {
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// TODO(bunnei): This will be used by the JIT in a subsequent commit
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}
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static Common::Profiling::TimingCategory shader_category("Vertex Shader");
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OutputVertex Run(UnitState& state, const InputVertex& input, int num_attributes) {
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auto& config = g_state.regs.vs;
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auto& setup = g_state.vs;
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Common::Profiling::ScopeTimer timer(shader_category);
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state.program_counter = config.main_offset;
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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// Setup input register table
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const auto& attribute_register_map = config.input_register_map;
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if (num_attributes > 0) state.input_registers[attribute_register_map.attribute0_register] = input.attr[0];
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if (num_attributes > 1) state.input_registers[attribute_register_map.attribute1_register] = input.attr[1];
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if (num_attributes > 2) state.input_registers[attribute_register_map.attribute2_register] = input.attr[2];
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if (num_attributes > 3) state.input_registers[attribute_register_map.attribute3_register] = input.attr[3];
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if (num_attributes > 4) state.input_registers[attribute_register_map.attribute4_register] = input.attr[4];
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if (num_attributes > 5) state.input_registers[attribute_register_map.attribute5_register] = input.attr[5];
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if (num_attributes > 6) state.input_registers[attribute_register_map.attribute6_register] = input.attr[6];
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if (num_attributes > 7) state.input_registers[attribute_register_map.attribute7_register] = input.attr[7];
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if (num_attributes > 8) state.input_registers[attribute_register_map.attribute8_register] = input.attr[8];
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if (num_attributes > 9) state.input_registers[attribute_register_map.attribute9_register] = input.attr[9];
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if (num_attributes > 10) state.input_registers[attribute_register_map.attribute10_register] = input.attr[10];
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if (num_attributes > 11) state.input_registers[attribute_register_map.attribute11_register] = input.attr[11];
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if (num_attributes > 12) state.input_registers[attribute_register_map.attribute12_register] = input.attr[12];
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if (num_attributes > 13) state.input_registers[attribute_register_map.attribute13_register] = input.attr[13];
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if (num_attributes > 14) state.input_registers[attribute_register_map.attribute14_register] = input.attr[14];
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if (num_attributes > 15) state.input_registers[attribute_register_map.attribute15_register] = input.attr[15];
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state.conditional_code[0] = false;
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state.conditional_code[1] = false;
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RunInterpreter(state);
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#if PICA_DUMP_SHADERS
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DebugUtils::DumpShader(setup.program_code.data(), state.debug.max_offset, setup.swizzle_data.data(),
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state.debug.max_opdesc_id, config.main_offset,
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g_state.regs.vs_output_attributes); // TODO: Don't hardcode VS here
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#endif
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// Setup output data
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OutputVertex ret;
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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for (int i = 0; i < 7; ++i) {
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const auto& output_register_map = g_state.regs.vs_output_attributes[i]; // TODO: Don't hardcode VS here
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u32 semantics[4] = {
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_z, output_register_map.map_w
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};
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for (int comp = 0; comp < 4; ++comp) {
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float24* out = ((float24*)&ret) + semantics[comp];
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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*out = state.output_registers[i][comp];
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} else {
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// Zero output so that attributes which aren't output won't have denormals in them,
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// which would slow us down later.
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memset(out, 0, sizeof(*out));
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}
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}
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}
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
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for (int i = 0; i < 4; ++i) {
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ret.color[i] = float24::FromFloat32(
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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}
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LOG_TRACE(Render_Software, "Output vertex: pos (%.2f, %.2f, %.2f, %.2f), col(%.2f, %.2f, %.2f, %.2f), tc0(%.2f, %.2f)",
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ret.pos.x.ToFloat32(), ret.pos.y.ToFloat32(), ret.pos.z.ToFloat32(), ret.pos.w.ToFloat32(),
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ret.color.x.ToFloat32(), ret.color.y.ToFloat32(), ret.color.z.ToFloat32(), ret.color.w.ToFloat32(),
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ret.tc0.u().ToFloat32(), ret.tc0.v().ToFloat32());
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return ret;
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}
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} // namespace Shader
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} // namespace Pica
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <boost/container/static_vector.hpp>
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#include <nihstro/shader_binary.h>
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "common/vector_math.h"
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#include "video_core/pica.h"
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using nihstro::RegisterType;
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using nihstro::SourceRegister;
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using nihstro::DestRegister;
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namespace Pica {
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namespace Shader {
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struct InputVertex {
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Math::Vec4<float24> attr[16];
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};
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struct OutputVertex {
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OutputVertex() = default;
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// VS output attributes
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Math::Vec4<float24> pos;
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Math::Vec4<float24> dummy; // quaternions (not implemented, yet)
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Math::Vec4<float24> color;
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Math::Vec2<float24> tc0;
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Math::Vec2<float24> tc1;
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float24 pad[6];
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Math::Vec2<float24> tc2;
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// Padding for optimal alignment
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float24 pad2[4];
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// Attributes used to store intermediate results
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// position after perspective divide
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Math::Vec3<float24> screenpos;
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float24 pad3;
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// Linear interpolation
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// factor: 0=this, 1=vtx
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void Lerp(float24 factor, const OutputVertex& vtx) {
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pos = pos * factor + vtx.pos * (float24::FromFloat32(1) - factor);
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// TODO: Should perform perspective correct interpolation here...
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tc0 = tc0 * factor + vtx.tc0 * (float24::FromFloat32(1) - factor);
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tc1 = tc1 * factor + vtx.tc1 * (float24::FromFloat32(1) - factor);
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tc2 = tc2 * factor + vtx.tc2 * (float24::FromFloat32(1) - factor);
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screenpos = screenpos * factor + vtx.screenpos * (float24::FromFloat32(1) - factor);
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color = color * factor + vtx.color * (float24::FromFloat32(1) - factor);
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}
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// Linear interpolation
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// factor: 0=v0, 1=v1
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static OutputVertex Lerp(float24 factor, const OutputVertex& v0, const OutputVertex& v1) {
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OutputVertex ret = v0;
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ret.Lerp(factor, v1);
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return ret;
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}
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};
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static_assert(std::is_pod<OutputVertex>::value, "Structure is not POD");
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static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has invalid size");
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/**
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* This structure contains the state information that needs to be unique for a shader unit. The 3DS
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* has four shader units that process shaders in parallel. At the present, Citra only implements a
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* single shader unit that processes all shaders serially. Putting the state information in a struct
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* here will make it easier for us to parallelize the shader processing later.
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*/
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struct UnitState {
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// The registers are accessed by the shader JIT using SSE instructions, and are therefore
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// required to be 16-byte aligned.
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Math::Vec4<float24> MEMORY_ALIGNED16(input_registers[16]);
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Math::Vec4<float24> MEMORY_ALIGNED16(output_registers[16]);
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Math::Vec4<float24> MEMORY_ALIGNED16(temporary_registers[16]);
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u32 program_counter;
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bool conditional_code[2];
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// Two Address registers and one loop counter
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// TODO: How many bits do these actually have?
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s32 address_registers[3];
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enum {
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INVALID_ADDRESS = 0xFFFFFFFF
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};
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struct CallStackElement {
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u32 final_address; // Address upon which we jump to return_address
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u32 return_address; // Where to jump when leaving scope
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u8 repeat_counter; // How often to repeat until this call stack element is removed
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u8 loop_increment; // Which value to add to the loop counter after an iteration
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// TODO: Should this be a signed value? Does it even matter?
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u32 loop_address; // The address where we'll return to after each loop iteration
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};
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// TODO: Is there a maximal size for this?
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boost::container::static_vector<CallStackElement, 16> call_stack;
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struct {
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u32 max_offset; // maximum program counter ever reached
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u32 max_opdesc_id; // maximum swizzle pattern index ever used
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} debug;
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static int InputOffset(const SourceRegister& reg) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Input:
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return (int)offsetof(UnitState, input_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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case RegisterType::Temporary:
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return (int)offsetof(UnitState, temporary_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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default:
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UNREACHABLE();
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return 0;
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}
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}
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static int OutputOffset(const DestRegister& reg) {
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switch (reg.GetRegisterType()) {
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case RegisterType::Output:
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return (int)offsetof(UnitState, output_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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case RegisterType::Temporary:
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return (int)offsetof(UnitState, temporary_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
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default:
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UNREACHABLE();
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return 0;
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}
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}
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};
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/**
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* Performs any shader unit setup that only needs to happen once per shader (as opposed to once per
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* vertex, which would happen within the `Run` function).
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* @param state Shader unit state, must be setup per shader and per shader unit
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*/
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void Setup(UnitState& state);
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/**
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* Runs the currently setup shader
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* @param state Shader unit state, must be setup per shader and per shader unit
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* @param input Input vertex into the shader
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* @param num_attributes The number of vertex shader attributes
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* @return The output vertex, after having been processed by the vertex shader
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*/
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OutputVertex Run(UnitState& state, const InputVertex& input, int num_attributes);
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} // namespace Shader
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} // namespace Pica
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