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Implement SetLcdForceBlack, move register enum to hw.h

master
archshift 2015-03-05 19:38:23 +07:00
parent 8e4e28aacb
commit 47010fea31
4 changed files with 69 additions and 36 deletions
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44
src/core/hle/service/gsp_gpu.cpp
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@ -7,7 +7,9 @@
#include "core/mem_map.h"
#include "core/hle/kernel/event.h"
#include "core/hle/kernel/shared_memory.h"
#include "core/hle/result.h"
#include "gsp_gpu.h"
#include "core/hw/hw.h"
#include "core/hw/gpu.h"
#include "video_core/gpu_debugger.h"
@ -85,7 +87,7 @@ static void WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
return;
while (size_in_bytes > 0) {
GPU::Write<u32>(base_address + 0x1EB00000, *data);
HW::Write<u32>(base_address + 0x1EB00000, *data);
size_in_bytes -= 4;
++data;
@ -131,12 +133,12 @@ static void WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, const u32*
const u32 reg_address = base_address + 0x1EB00000;
u32 reg_value;
GPU::Read<u32>(reg_value, reg_address);
HW::Read<u32>(reg_value, reg_address);
// Update the current value of the register only for set mask bits
reg_value = (reg_value & ~*masks) | (*data | *masks);
GPU::Write<u32>(reg_address, reg_value);
HW::Write<u32>(reg_address, reg_value);
size_in_bytes -= 4;
++data;
@ -188,7 +190,7 @@ static void ReadHWRegs(Service::Interface* self) {
u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
while (size > 0) {
GPU::Read<u32>(*dst, reg_addr + 0x1EB00000);
HW::Read<u32>(*dst, reg_addr + 0x1EB00000);
size -= 4;
++dst;
@ -427,6 +429,38 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
}
}
/**
* GSP_GPU::SetLcdForceBlack service function
*
* Enable or disable REG_LCDCOLORFILL with the color black.
*
* Inputs:
* 1: Black color fill flag (0 = don't fill, !0 = fill)
* Outputs:
* 1: Result code
*/
void SetLcdForceBlack(Service::Interface* self) {
// TODO: currently has no effect, as LCD reg writes have nowhere to go.
u32* cmd_buff = Kernel::GetCommandBuffer();
bool enable_black = cmd_buff[1] != 0;
u32 data = 0;
if (enable_black) {
// Sets bit 24 to 1, enabling the fill
// Since data is already 0x00000000, there is no need to explicitly set
// bits 0-23 to zero (black), or bit 24 to 0 (fill disabled).
data |= (1 << 24);
}
u32 data_main = data;
u32 data_sub = data;
WriteHWRegs(0x202204, 4, &data_main); // Main LCD
WriteHWRegs(0x202A04, 4, &data_sub); // Sub LCD
cmd_buff[1] = RESULT_SUCCESS.raw;
}
/// This triggers handling of the GX command written to the command buffer in shared memory.
static void TriggerCmdReqQueue(Service::Interface* self) {
// Iterate through each thread's command queue...
@ -460,7 +494,7 @@ const Interface::FunctionInfo FunctionTable[] = {
{0x00080082, FlushDataCache, "FlushDataCache"},
{0x00090082, nullptr, "InvalidateDataCache"},
{0x000A0044, nullptr, "RegisterInterruptEvents"},
{0x000B0040, nullptr, "SetLcdForceBlack"},
{0x000B0040, SetLcdForceBlack, "SetLcdForceBlack"},
{0x000C0000, TriggerCmdReqQueue, "TriggerCmdReqQueue"},
{0x000D0140, nullptr, "SetDisplayTransfer"},
{0x000E0180, nullptr, "SetTextureCopy"},

9
src/core/hw/gpu.cpp
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@ -15,12 +15,13 @@
#include "core/hle/service/gsp_gpu.h"
#include "core/hle/service/dsp_dsp.h"
#include "core/hw/hw.h"
#include "core/hw/gpu.h"
#include "video_core/command_processor.h"
#include "video_core/utils.h"
#include "video_core/video_core.h"
#include <video_core/color.h>
#include "video_core/color.h"
namespace GPU {
@ -40,7 +41,7 @@ static bool last_skip_frame = false;
template <typename T>
inline void Read(T &var, const u32 raw_addr) {
u32 addr = raw_addr - 0x1EF00000;
u32 addr = raw_addr - HW::VADDR_GPU;
u32 index = addr / 4;
// Reads other than u32 are untested, so I'd rather have them abort than silently fail
@ -54,7 +55,7 @@ inline void Read(T &var, const u32 raw_addr) {
template <typename T>
inline void Write(u32 addr, const T data) {
addr -= 0x1EF00000;
addr -= HW::VADDR_GPU;
u32 index = addr / 4;
// Writes other than u32 are untested, so I'd rather have them abort than silently fail
@ -313,8 +314,6 @@ void Init() {
framebuffer_top.address_right2 = 0x182B9800;
framebuffer_sub.address_left1 = 0x1848F000;
framebuffer_sub.address_left2 = 0x184C7800;
//framebuffer_sub.address_right1 = unknown;
//framebuffer_sub.address_right2 = unknown;
framebuffer_top.width = 240;
framebuffer_top.height = 400;

26
src/core/hw/hw.cpp
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@ -9,32 +9,6 @@
namespace HW {
enum {
VADDR_HASH = 0x1EC01000,
VADDR_CSND = 0x1EC03000,
VADDR_DSP = 0x1EC40000,
VADDR_PDN = 0x1EC41000,
VADDR_CODEC = 0x1EC41000,
VADDR_SPI = 0x1EC42000,
VADDR_SPI_2 = 0x1EC43000, // Only used under TWL_FIRM?
VADDR_I2C = 0x1EC44000,
VADDR_CODEC_2 = 0x1EC45000,
VADDR_HID = 0x1EC46000,
VADDR_PAD = 0x1EC46000,
VADDR_PTM = 0x1EC46000,
VADDR_GPIO = 0x1EC47000,
VADDR_I2C_2 = 0x1EC48000,
VADDR_SPI_3 = 0x1EC60000,
VADDR_I2C_3 = 0x1EC61000,
VADDR_MIC = 0x1EC62000,
VADDR_PXI = 0x1EC63000, // 0xFFFD2000
//VADDR_NTRCARD
VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info
VADDR_DSP_2 = 0x1ED03000,
VADDR_HASH_2 = 0x1EE01000,
VADDR_GPU = 0x1EF00000,
};
template <typename T>
inline void Read(T &var, const u32 addr) {
switch (addr & 0xFFFFF000) {

26
src/core/hw/hw.h
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@ -8,6 +8,32 @@
namespace HW {
enum {
VADDR_IO = 0x1EC00000,
VADDR_HASH = 0x1EC01000,
VADDR_CSND = 0x1EC03000,
VADDR_DSP = 0x1EC40000,
VADDR_PDN = 0x1EC41000,
VADDR_CODEC = 0x1EC41000,
VADDR_SPI = 0x1EC42000,
VADDR_SPI_2 = 0x1EC43000, // Only used under TWL_FIRM?
VADDR_I2C = 0x1EC44000,
VADDR_CODEC_2 = 0x1EC45000,
VADDR_HID = 0x1EC46000,
VADDR_GPIO = 0x1EC47000,
VADDR_I2C_2 = 0x1EC48000,
VADDR_SPI_3 = 0x1EC60000,
VADDR_I2C_3 = 0x1EC61000,
VADDR_MIC = 0x1EC62000,
VADDR_PXI = 0x1EC63000, // 0xFFFD2000
//VADDR_NTRCARD
VADDR_CDMA = 0xFFFDA000, // CoreLink DMA-330? Info
VADDR_LCD = 0x1ED02000,
VADDR_DSP_2 = 0x1ED03000,
VADDR_HASH_2 = 0x1EE01000,
VADDR_GPU = 0x1EF00000,
};
template <typename T>
void Read(T &var, const u32 addr);