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@ -45,6 +45,18 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
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}
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}
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break;
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break;
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}
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}
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case OpCode::Id::IPA: {
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const auto& attribute = instr.attribute.fmt28;
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const Tegra::Shader::IpaMode input_mode{instr.ipa.interp_mode.Value(),
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instr.ipa.sample_mode.Value()};
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const Node input_attr = GetInputAttribute(attribute.index, attribute.element, input_mode);
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const Node ipa = Operation(OperationCode::Ipa, input_attr);
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const Node value = GetSaturatedFloat(ipa, instr.ipa.saturate);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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default:
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default:
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UNIMPLEMENTED_MSG("Unhandled instruction: {}", opcode->get().GetName());
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UNIMPLEMENTED_MSG("Unhandled instruction: {}", opcode->get().GetName());
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}
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}
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