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@ -62,6 +62,20 @@ u32 GetMemorySize(Tegra::Shader::UniformType uniform_type) {
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}
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}
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Node ExtractUnaligned(Node value, Node address, u32 mask, u32 size) {
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Node offset = Operation(OperationCode::UBitwiseAnd, address, Immediate(mask));
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offset = Operation(OperationCode::ULogicalShiftLeft, std::move(offset), Immediate(3));
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return Operation(OperationCode::UBitfieldExtract, std::move(value), std::move(offset),
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Immediate(size));
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}
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Node InsertUnaligned(Node dest, Node value, Node address, u32 mask, u32 size) {
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Node offset = Operation(OperationCode::UBitwiseAnd, std::move(address), Immediate(mask));
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offset = Operation(OperationCode::ULogicalShiftLeft, std::move(offset), Immediate(3));
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return Operation(OperationCode::UBitfieldInsert, std::move(dest), std::move(value),
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std::move(offset), Immediate(size));
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}
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Node Sign16Extend(Node value) {
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Node sign = Operation(OperationCode::UBitwiseAnd, value, Immediate(1U << 15));
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Node is_sign = Operation(OperationCode::LogicalUEqual, std::move(sign), Immediate(1U << 15));
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@ -144,19 +158,23 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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LOG_DEBUG(HW_GPU, "LD_L cache management mode: {}", static_cast<u64>(instr.ld_l.unknown));
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[[fallthrough]];
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case OpCode::Id::LD_S: {
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const auto GetMemory = [&](s32 offset) {
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const auto GetAddress = [&](s32 offset) {
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ASSERT(offset % 4 == 0);
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const Node immediate_offset = Immediate(static_cast<s32>(instr.smem_imm) + offset);
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const Node address =
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Operation(OperationCode::IAdd, GetRegister(instr.gpr8), immediate_offset);
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return opcode->get().GetId() == OpCode::Id::LD_S ? GetSharedMemory(address)
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: GetLocalMemory(address);
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return Operation(OperationCode::IAdd, GetRegister(instr.gpr8), immediate_offset);
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};
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const auto GetMemory = [&](s32 offset) {
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return opcode->get().GetId() == OpCode::Id::LD_S ? GetSharedMemory(GetAddress(offset))
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: GetLocalMemory(GetAddress(offset));
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};
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switch (instr.ldst_sl.type.Value()) {
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case StoreType::Signed16:
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case StoreType::Signed16: {
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Node address = GetAddress(0);
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SetRegister(bb, instr.gpr0, Sign16Extend(GetMemory(0)));
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break;
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}
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case StoreType::Bits32:
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case StoreType::Bits64:
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case StoreType::Bits128: {
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@ -223,12 +241,7 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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// To handle unaligned loads get the bytes used to dereference global memory and extract
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// those bytes from the loaded u32.
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if (IsUnaligned(type)) {
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Node mask = Immediate(GetUnalignedMask(type));
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Node offset = Operation(OperationCode::UBitwiseAnd, real_address, std::move(mask));
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offset = Operation(OperationCode::ULogicalShiftLeft, offset, Immediate(3));
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gmem = Operation(OperationCode::UBitfieldExtract, std::move(gmem),
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std::move(offset), Immediate(size));
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gmem = ExtractUnaligned(gmem, real_address, GetUnalignedMask(type), size);
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}
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SetTemporary(bb, i, gmem);
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@ -334,12 +347,8 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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Node value = GetRegister(instr.gpr0.Value() + i);
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if (IsUnaligned(type)) {
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Node mask = Immediate(GetUnalignedMask(type));
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Node offset = Operation(OperationCode::UBitwiseAnd, real_address, std::move(mask));
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offset = Operation(OperationCode::ULogicalShiftLeft, offset, Immediate(3));
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value = Operation(OperationCode::UBitfieldInsert, gmem, std::move(value), offset,
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Immediate(size));
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const u32 mask = GetUnalignedMask(type);
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value = InsertUnaligned(gmem, std::move(value), real_address, mask, size);
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}
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bb.push_back(Operation(OperationCode::Assign, gmem, value));
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