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@ -260,14 +260,14 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
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// The "mov" instruction ignores the first operand (rn).
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rn_str[0] = 0;
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if ((flags & kNoOperand1) == 0) {
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rn_str = StringFromFormat("r%d, ", rn);
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rn_str = Common::StringFromFormat("r%d, ", rn);
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}
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// The following instructions do not write the result register (rd):
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// tst, teq, cmp, cmn.
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rd_str[0] = 0;
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if ((flags & kNoDest) == 0) {
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rd_str = StringFromFormat("r%d, ", rd);
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rd_str = Common::StringFromFormat("r%d, ", rd);
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}
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const char *sbit_str = "";
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@ -275,7 +275,7 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
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sbit_str = "s";
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if (is_immed) {
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return StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x",
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return Common::StringFromFormat("%s%s%s\t%s%s#%u ; 0x%x",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), immed, immed);
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}
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@ -290,24 +290,24 @@ std::string ARM_Disasm::DisassembleALU(Opcode opcode, uint32_t insn)
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rotated_val = (rotated_val >> rotate2) | (rotated_val << (32 - rotate2));
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if (!shift_is_reg && shift_type == 0 && shift_amount == 0) {
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return StringFromFormat("%s%s%s\t%s%sr%d",
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return Common::StringFromFormat("%s%s%s\t%s%sr%d",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm);
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}
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const char *shift_name = shift_names[shift_type];
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if (shift_is_reg) {
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return StringFromFormat("%s%s%s\t%s%sr%d, %s r%d",
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return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s r%d",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm,
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shift_name, rs);
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}
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if (shift_amount == 0) {
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if (shift_type == 3) {
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return StringFromFormat("%s%s%s\t%s%sr%d, RRX",
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return Common::StringFromFormat("%s%s%s\t%s%sr%d, RRX",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm);
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}
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shift_amount = 32;
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}
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return StringFromFormat("%s%s%s\t%s%sr%d, %s #%u",
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return Common::StringFromFormat("%s%s%s\t%s%sr%d, %s #%u",
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opname, cond_to_str(cond), sbit_str, rd_str.c_str(), rn_str.c_str(), rm,
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shift_name, shift_amount);
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}
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@ -325,20 +325,20 @@ std::string ARM_Disasm::DisassembleBranch(uint32_t addr, Opcode opcode, uint32_t
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offset += 8;
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addr += offset;
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const char *opname = opcode_names[opcode];
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return StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr);
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return Common::StringFromFormat("%s%s\t0x%x", opname, cond_to_str(cond), addr);
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}
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std::string ARM_Disasm::DisassembleBX(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rn = insn & 0xf;
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return StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn);
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return Common::StringFromFormat("bx%s\tr%d", cond_to_str(cond), rn);
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}
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std::string ARM_Disasm::DisassembleBKPT(uint32_t insn)
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{
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uint32_t immed = (((insn >> 8) & 0xfff) << 4) | (insn & 0xf);
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return StringFromFormat("bkpt\t#%d", immed);
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return Common::StringFromFormat("bkpt\t#%d", immed);
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}
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std::string ARM_Disasm::DisassembleCLZ(uint32_t insn)
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@ -346,7 +346,7 @@ std::string ARM_Disasm::DisassembleCLZ(uint32_t insn)
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uint8_t cond = (insn >> 28) & 0xf;
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uint8_t rd = (insn >> 12) & 0xf;
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uint8_t rm = insn & 0xf;
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return StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
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return Common::StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
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}
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std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
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@ -376,7 +376,7 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
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tmp_list[0] = 0;
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for (int ii = 0; ii < 16; ++ii) {
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if (reg_list & (1 << ii)) {
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tmp_list += StringFromFormat("%sr%d", comma, ii);
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tmp_list += Common::StringFromFormat("%sr%d", comma, ii);
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comma = ",";
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}
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}
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@ -396,7 +396,7 @@ std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
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}
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}
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return StringFromFormat("%s%s%s\tr%d%s, {%s}%s",
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return Common::StringFromFormat("%s%s%s\tr%d%s, {%s}%s",
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opname, cond_to_str(cond), addr_mode, rn, bang, tmp_list.c_str(), carret);
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}
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@ -432,10 +432,10 @@ std::string ARM_Disasm::DisassembleMem(uint32_t insn)
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if (is_reg == 0) {
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if (is_pre) {
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if (offset == 0) {
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return StringFromFormat("%s%s%s\tr%d, [r%d]",
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return Common::StringFromFormat("%s%s%s\tr%d, [r%d]",
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opname, cond_to_str(cond), byte, rd, rn);
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} else {
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return StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s",
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return Common::StringFromFormat("%s%s%s\tr%d, [r%d, #%s%u]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, offset, bang);
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}
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} else {
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@ -443,7 +443,7 @@ std::string ARM_Disasm::DisassembleMem(uint32_t insn)
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if (write_back)
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transfer = "t";
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return StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u",
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return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], #%s%u",
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opname, cond_to_str(cond), byte, transfer, rd, rn, minus, offset);
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}
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}
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@ -457,16 +457,16 @@ std::string ARM_Disasm::DisassembleMem(uint32_t insn)
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if (is_pre) {
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if (shift_amount == 0) {
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if (shift_type == 0) {
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return StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s",
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return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang);
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}
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if (shift_type == 3) {
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return StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s",
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return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, RRX]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, rm, bang);
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}
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shift_amount = 32;
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}
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return StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s",
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return Common::StringFromFormat("%s%s%s\tr%d, [r%d, %sr%d, %s #%u]%s",
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opname, cond_to_str(cond), byte, rd, rn, minus, rm,
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shift_name, shift_amount, bang);
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}
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@ -477,17 +477,17 @@ std::string ARM_Disasm::DisassembleMem(uint32_t insn)
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if (shift_amount == 0) {
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if (shift_type == 0) {
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return StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d",
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return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d",
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opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
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}
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if (shift_type == 3) {
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return StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX",
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return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, RRX",
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opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm);
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}
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shift_amount = 32;
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}
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return StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u",
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return Common::StringFromFormat("%s%s%s%s\tr%d, [r%d], %sr%d, %s #%u",
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opname, cond_to_str(cond), byte, transfer, rd, rn, minus, rm,
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shift_name, shift_amount);
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}
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@ -528,22 +528,22 @@ std::string ARM_Disasm::DisassembleMemHalf(uint32_t insn)
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if (is_immed) {
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if (is_pre) {
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if (offset == 0) {
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return StringFromFormat("%s%sh\tr%d, [r%d]", opname, cond_to_str(cond), rd, rn);
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return Common::StringFromFormat("%s%sh\tr%d, [r%d]", opname, cond_to_str(cond), rd, rn);
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} else {
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return StringFromFormat("%s%sh\tr%d, [r%d, #%s%u]%s",
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return Common::StringFromFormat("%s%sh\tr%d, [r%d, #%s%u]%s",
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opname, cond_to_str(cond), rd, rn, minus, offset, bang);
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}
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} else {
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return StringFromFormat("%s%sh\tr%d, [r%d], #%s%u",
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return Common::StringFromFormat("%s%sh\tr%d, [r%d], #%s%u",
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opname, cond_to_str(cond), rd, rn, minus, offset);
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}
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}
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if (is_pre) {
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return StringFromFormat("%s%sh\tr%d, [r%d, %sr%d]%s",
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return Common::StringFromFormat("%s%sh\tr%d, [r%d, %sr%d]%s",
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opname, cond_to_str(cond), rd, rn, minus, rm, bang);
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} else {
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return StringFromFormat("%s%sh\tr%d, [r%d], %sr%d",
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return Common::StringFromFormat("%s%sh\tr%d, [r%d], %sr%d",
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opname, cond_to_str(cond), rd, rn, minus, rm);
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}
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}
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@ -558,7 +558,7 @@ std::string ARM_Disasm::DisassembleMCR(Opcode opcode, uint32_t insn)
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uint8_t crm = insn & 0xf;
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const char *opname = opcode_names[opcode];
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return StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}",
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return Common::StringFromFormat("%s%s\t%d, 0, r%d, cr%d, cr%d, {%d}",
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opname, cond_to_str(cond), cpnum, crd, crn, crm, opcode2);
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}
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@ -572,7 +572,7 @@ std::string ARM_Disasm::DisassembleMLA(Opcode opcode, uint32_t insn)
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uint8_t bit_s = (insn >> 20) & 1;
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const char *opname = opcode_names[opcode];
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return StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
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return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
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opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs, rn);
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}
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@ -586,7 +586,7 @@ std::string ARM_Disasm::DisassembleUMLAL(Opcode opcode, uint32_t insn)
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uint8_t bit_s = (insn >> 20) & 1;
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const char *opname = opcode_names[opcode];
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return StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
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return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d, r%d",
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opname, cond_to_str(cond), bit_s ? "s" : "", rdlo, rdhi, rm, rs);
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}
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@ -599,7 +599,7 @@ std::string ARM_Disasm::DisassembleMUL(Opcode opcode, uint32_t insn)
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uint8_t bit_s = (insn >> 20) & 1;
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const char *opname = opcode_names[opcode];
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return StringFromFormat("%s%s%s\tr%d, r%d, r%d",
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return Common::StringFromFormat("%s%s%s\tr%d, r%d, r%d",
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opname, cond_to_str(cond), bit_s ? "s" : "", rd, rm, rs);
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}
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@ -609,7 +609,7 @@ std::string ARM_Disasm::DisassembleMRS(uint32_t insn)
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uint8_t rd = (insn >> 12) & 0xf;
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uint8_t ps = (insn >> 22) & 1;
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return StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
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return Common::StringFromFormat("mrs%s\tr%d, %s", cond_to_str(cond), rd, ps ? "spsr" : "cpsr");
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}
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std::string ARM_Disasm::DisassembleMSR(uint32_t insn)
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@ -636,13 +636,13 @@ std::string ARM_Disasm::DisassembleMSR(uint32_t insn)
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uint8_t rotate = (insn >> 8) & 0xf;
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uint8_t rotate2 = rotate << 1;
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uint32_t rotated_val = (immed >> rotate2) | (immed << (32 - rotate2));
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return StringFromFormat("msr%s\t%s_%s, #0x%x",
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return Common::StringFromFormat("msr%s\t%s_%s, #0x%x",
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cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rotated_val);
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}
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uint8_t rm = insn & 0xf;
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return StringFromFormat("msr%s\t%s_%s, r%d",
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return Common::StringFromFormat("msr%s\t%s_%s, r%d",
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cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm);
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}
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@ -658,14 +658,14 @@ std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
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if (is_reg) {
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uint8_t rm = insn & 0xf;
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return StringFromFormat("pld\t[r%d, %sr%d]", rn, minus, rm);
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return Common::StringFromFormat("pld\t[r%d, %sr%d]", rn, minus, rm);
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}
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uint16_t offset = insn & 0xfff;
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if (offset == 0) {
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return StringFromFormat("pld\t[r%d]", rn);
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return Common::StringFromFormat("pld\t[r%d]", rn);
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} else {
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return StringFromFormat("pld\t[r%d, #%s%u]", rn, minus, offset);
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return Common::StringFromFormat("pld\t[r%d, #%s%u]", rn, minus, offset);
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}
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}
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@ -674,7 +674,7 @@ std::string ARM_Disasm::DisassembleSWI(uint32_t insn)
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uint8_t cond = (insn >> 28) & 0xf;
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uint32_t sysnum = insn & 0x00ffffff;
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return StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum);
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return Common::StringFromFormat("swi%s 0x%x", cond_to_str(cond), sysnum);
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}
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std::string ARM_Disasm::DisassembleSWP(Opcode opcode, uint32_t insn)
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@ -685,7 +685,7 @@ std::string ARM_Disasm::DisassembleSWP(Opcode opcode, uint32_t insn)
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uint8_t rm = insn & 0xf;
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const char *opname = opcode_names[opcode];
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return StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
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return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opname, cond_to_str(cond), rd, rm, rn);
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}
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Opcode ARM_Disasm::Decode(uint32_t insn) {
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