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@ -924,27 +924,93 @@ private:
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}
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Id Branch(Operation operation) {
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UNIMPLEMENTED();
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const auto target = std::get_if<ImmediateNode>(operation[0]);
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UNIMPLEMENTED_IF(!target);
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Emit(OpStore(jmp_to, Constant(t_uint, target->GetValue())));
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BranchingOp([&]() { Emit(OpBranch(continue_label)); });
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return {};
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}
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Id PushFlowStack(Operation operation) {
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UNIMPLEMENTED();
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const auto target = std::get_if<ImmediateNode>(operation[0]);
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ASSERT(target);
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const Id current = Emit(OpLoad(t_uint, flow_stack_top));
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const Id next = Emit(OpIAdd(t_uint, current, Constant(t_uint, 1)));
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const Id access = Emit(OpAccessChain(t_func_uint, flow_stack, current));
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Emit(OpStore(access, Constant(t_uint, target->GetValue())));
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Emit(OpStore(flow_stack_top, next));
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return {};
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}
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Id PopFlowStack(Operation operation) {
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UNIMPLEMENTED();
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const Id current = Emit(OpLoad(t_uint, flow_stack_top));
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const Id previous = Emit(OpISub(t_uint, current, Constant(t_uint, 1)));
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const Id access = Emit(OpAccessChain(t_func_uint, flow_stack, previous));
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const Id target = Emit(OpLoad(t_uint, access));
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Emit(OpStore(flow_stack_top, previous));
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Emit(OpStore(jmp_to, target));
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BranchingOp([&]() { Emit(OpBranch(continue_label)); });
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return {};
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}
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Id Exit(Operation operation) {
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UNIMPLEMENTED();
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switch (stage) {
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case ShaderStage::Vertex: {
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// TODO(Rodrigo): We should use VK_EXT_depth_range_unrestricted instead, but it doesn't
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// seem to be working on Nvidia's drivers and Intel (mesa and blob) doesn't support it.
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const Id position = AccessElement(t_float4, per_vertex, position_index);
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Id depth = Emit(OpLoad(t_float, AccessElement(t_out_float, position, 2)));
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depth = Emit(OpFAdd(t_float, depth, Constant(t_float, 1.0f)));
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depth = Emit(OpFMul(t_float, depth, Constant(t_float, 0.5f)));
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Emit(OpStore(AccessElement(t_out_float, position, 2), depth));
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break;
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}
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case ShaderStage::Fragment: {
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const auto SafeGetRegister = [&](u32 reg) {
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// TODO(Rodrigo): Replace with contains once C++20 releases
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if (const auto it = registers.find(reg); it != registers.end()) {
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return Emit(OpLoad(t_float, it->second));
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}
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return Constant(t_float, 0.0f);
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};
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UNIMPLEMENTED_IF_MSG(header.ps.omap.sample_mask != 0,
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"Sample mask write is unimplemented");
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// TODO(Rodrigo): Alpha testing
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// Write the color outputs using the data in the shader registers, disabled
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// rendertargets/components are skipped in the register assignment.
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u32 current_reg = 0;
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for (u32 rt = 0; rt < Maxwell::NumRenderTargets; ++rt) {
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// TODO(Subv): Figure out how dual-source blending is configured in the Switch.
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for (u32 component = 0; component < 4; ++component) {
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if (header.ps.IsColorComponentOutputEnabled(rt, component)) {
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Emit(OpStore(AccessElement(t_out_float, frag_colors.at(rt), component),
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SafeGetRegister(current_reg)));
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++current_reg;
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}
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}
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}
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if (header.ps.omap.depth) {
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// The depth output is always 2 registers after the last color output, and
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// current_reg already contains one past the last color register.
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Emit(OpStore(frag_depth, SafeGetRegister(current_reg + 1)));
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}
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break;
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}
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}
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BranchingOp([&]() { Emit(OpReturn()); });
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return {};
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}
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Id Discard(Operation operation) {
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UNIMPLEMENTED();
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BranchingOp([&]() { Emit(OpKill()); });
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return {};
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}
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@ -1067,6 +1133,17 @@ private:
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return {};
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}
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void BranchingOp(std::function<void()> call) {
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const Id true_label = OpLabel();
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const Id skip_label = OpLabel();
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Emit(OpSelectionMerge(skip_label, spv::SelectionControlMask::Flatten));
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Emit(OpBranchConditional(v_true, true_label, skip_label, 1, 0));
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Emit(true_label);
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call();
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Emit(skip_label);
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}
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static constexpr OperationDecompilersArray operation_decompilers = {
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&SPIRVDecompiler::Assign,
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