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@ -48,6 +48,12 @@ public:
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CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Read);
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return memory.Read64(vaddr);
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}
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std::optional<u32> MemoryReadCode(u32 vaddr) override {
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if (!memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
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return std::nullopt;
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}
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return MemoryRead32(vaddr);
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}
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void MemoryWrite8(u32 vaddr, u8 value) override {
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if (CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write)) {
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@ -89,21 +95,28 @@ public:
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void InterpreterFallback(u32 pc, std::size_t num_instructions) override {
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parent.LogBacktrace();
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UNIMPLEMENTED_MSG("This should never happen, pc = {:08X}, code = {:08X}", pc,
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MemoryReadCode(pc));
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LOG_ERROR(Core_ARM,
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"Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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num_instructions, MemoryRead32(pc));
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}
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void ExceptionRaised(u32 pc, Dynarmic::A32::Exception exception) override {
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if (debugger_enabled) {
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parent.SaveContext(parent.breakpoint_context);
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parent.jit.load()->HaltExecution(ARM_Interface::breakpoint);
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switch (exception) {
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case Dynarmic::A32::Exception::NoExecuteFault:
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LOG_CRITICAL(Core_ARM, "Cannot execute instruction at unmapped address {:#08x}", pc);
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ReturnException(pc, ARM_Interface::no_execute);
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return;
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}
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default:
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if (debugger_enabled) {
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ReturnException(pc, ARM_Interface::breakpoint);
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return;
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}
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parent.LogBacktrace();
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LOG_CRITICAL(Core_ARM,
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"ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X}, thumb = {})",
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exception, pc, MemoryReadCode(pc), parent.IsInThumbMode());
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parent.LogBacktrace();
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LOG_CRITICAL(Core_ARM,
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"ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X}, thumb = {})",
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exception, pc, MemoryRead32(pc), parent.IsInThumbMode());
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}
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}
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void CallSVC(u32 swi) override {
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@ -141,15 +154,20 @@ public:
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const auto match{parent.MatchingWatchpoint(addr, size, type)};
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if (match) {
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parent.SaveContext(parent.breakpoint_context);
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parent.jit.load()->HaltExecution(ARM_Interface::watchpoint);
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parent.halted_watchpoint = match;
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ReturnException(parent.jit.load()->Regs()[15], ARM_Interface::watchpoint);
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return false;
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}
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return true;
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}
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void ReturnException(u32 pc, Dynarmic::HaltReason hr) {
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parent.SaveContext(parent.breakpoint_context);
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parent.breakpoint_context.cpu_registers[15] = pc;
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parent.jit.load()->HaltExecution(hr);
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}
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ARM_Dynarmic_32& parent;
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Core::Memory::Memory& memory;
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std::size_t num_interpreted_instructions{};
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