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@ -1848,9 +1848,16 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index)
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inst_base->br = NON_BRANCH;
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inst_base->br = NON_BRANCH;
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inst_cream->inst = inst;
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inst_cream->inst = inst;
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if (I_BIT == 0) {
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if (BITS(inst, 25, 27) == 2) {
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inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
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inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
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} else if (BITS(inst, 25, 27) == 3) {
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inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed);
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} else {
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} else {
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// Reaching this would indicate the thumb version
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// of this instruction, however the 3DS CPU doesn't
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// support this variant (the 3DS CPU is only ARMv6K,
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// while this variant is added in ARMv6T2).
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// So it's sufficient for citra to not implement this.
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DEBUG_MSG;
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DEBUG_MSG;
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}
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}
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@ -2800,9 +2807,16 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index)
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inst_base->br = NON_BRANCH;
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inst_base->br = NON_BRANCH;
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inst_cream->inst = inst;
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inst_cream->inst = inst;
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if (I_BIT == 0) {
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if (BITS(inst, 25, 27) == 2) {
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inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
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inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
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} else if (BITS(inst, 25, 27) == 3) {
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inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed);
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} else {
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} else {
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// Reaching this would indicate the thumb version
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// of this instruction, however the 3DS CPU doesn't
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// support this variant (the 3DS CPU is only ARMv6K,
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// while this variant is added in ARMv6T2).
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// So it's sufficient for citra to not implement this.
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DEBUG_MSG;
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DEBUG_MSG;
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}
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}
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