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@ -412,7 +412,8 @@ unsigned xscale_cp15_write_reg (ARMul_State * state, unsigned reg,
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return 0;
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}
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int xscale_cp15_init (ARMul_State * state)
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unsigned
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xscale_cp15_init (ARMul_State * state)
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{
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xscale_mmu_desc_t *desc;
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cache_desc_t *c_desc;
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@ -489,7 +490,8 @@ int xscale_cp15_init (ARMul_State * state)
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return -1;
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}
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void xscale_cp15_exit (ARMul_State * state)
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unsigned
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xscale_cp15_exit (ARMul_State * state)
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{
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//mmu_rb_exit(RB());
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mmu_wb_exit (WB ());
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@ -498,6 +500,7 @@ void xscale_cp15_exit (ARMul_State * state)
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mmu_tlb_exit (D_TLB ());
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mmu_cache_exit (I_CACHE ());
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mmu_tlb_exit (I_TLB ());
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return 0;
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};
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@ -1372,17 +1375,17 @@ static int xscale_mmu_v2p_dbct (ARMul_State * state, ARMword virt_addr,
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//AJ2D--------------------------------------------------------------------------
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/*xscale mmu_ops_t*/
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mmu_ops_t xscale_mmu_ops = {
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xscale_cp15_init,
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xscale_cp15_exit,
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xscale_mmu_read_byte,
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xscale_mmu_write_byte,
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xscale_mmu_read_halfword,
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xscale_mmu_write_halfword,
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xscale_mmu_read_word,
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xscale_mmu_write_word,
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xscale_mmu_load_instr, xscale_mmu_mcr, xscale_mmu_mrc,
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//teawater add for arm2x86 2005.06.24-------------------------------------------
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xscale_mmu_v2p_dbct,
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//AJ2D--------------------------------------------------------------------------
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};
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//mmu_ops_t xscale_mmu_ops = {
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// xscale_cp15_init,
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// xscale_cp15_exit,
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// xscale_mmu_read_byte,
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// xscale_mmu_write_byte,
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// xscale_mmu_read_halfword,
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// xscale_mmu_write_halfword,
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// xscale_mmu_read_word,
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// xscale_mmu_write_word,
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// xscale_mmu_load_instr, xscale_mmu_mcr, xscale_mmu_mrc,
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////teawater add for arm2x86 2005.06.24-------------------------------------------
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// xscale_mmu_v2p_dbct,
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////AJ2D--------------------------------------------------------------------------
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//};
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