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@ -226,7 +226,8 @@ struct Regs {
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Texture1 = 0x4,
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Texture2 = 0x5,
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Texture3 = 0x6,
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// 0x7-0xc = primary color??
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PreviousBuffer = 0xd,
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Constant = 0xe,
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Previous = 0xf,
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};
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@ -309,11 +310,36 @@ struct Regs {
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TevStageConfig tev_stage2;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage3;
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INSERT_PADDING_WORDS(0x13);
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INSERT_PADDING_WORDS(0x3);
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union {
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// Tev stages 0-3 write their output to the combiner buffer if the corresponding bit in
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// these masks are set
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BitField< 8, 4, u32> update_mask_rgb;
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BitField<12, 4, u32> update_mask_a;
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bool TevStageUpdatesCombinerBufferColor(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_rgb & (1 << stage_index));
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}
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bool TevStageUpdatesCombinerBufferAlpha(unsigned stage_index) const {
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return (stage_index < 4) && (update_mask_a & (1 << stage_index));
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}
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} tev_combiner_buffer_input;
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INSERT_PADDING_WORDS(0xf);
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TevStageConfig tev_stage4;
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INSERT_PADDING_WORDS(0x3);
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TevStageConfig tev_stage5;
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INSERT_PADDING_WORDS(0x3);
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union {
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BitField< 0, 8, u32> r;
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BitField< 8, 8, u32> g;
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BitField<16, 8, u32> b;
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BitField<24, 8, u32> a;
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} tev_combiner_buffer_color;
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INSERT_PADDING_WORDS(0x2);
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const std::array<Regs::TevStageConfig,6> GetTevStages() const {
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return { tev_stage0, tev_stage1,
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@ -784,8 +810,10 @@ struct Regs {
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ADD_FIELD(tev_stage1);
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ADD_FIELD(tev_stage2);
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ADD_FIELD(tev_stage3);
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ADD_FIELD(tev_combiner_buffer_input);
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ADD_FIELD(tev_stage4);
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ADD_FIELD(tev_stage5);
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ADD_FIELD(tev_combiner_buffer_color);
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ADD_FIELD(output_merger);
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ADD_FIELD(framebuffer);
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ADD_FIELD(vertex_attributes);
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@ -859,8 +887,10 @@ ASSERT_REG_POSITION(tev_stage0, 0xc0);
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ASSERT_REG_POSITION(tev_stage1, 0xc8);
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ASSERT_REG_POSITION(tev_stage2, 0xd0);
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ASSERT_REG_POSITION(tev_stage3, 0xd8);
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ASSERT_REG_POSITION(tev_combiner_buffer_input, 0xe0);
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ASSERT_REG_POSITION(tev_stage4, 0xf0);
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ASSERT_REG_POSITION(tev_stage5, 0xf8);
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ASSERT_REG_POSITION(tev_combiner_buffer_color, 0xfd);
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ASSERT_REG_POSITION(output_merger, 0x100);
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ASSERT_REG_POSITION(framebuffer, 0x110);
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ASSERT_REG_POSITION(vertex_attributes, 0x200);
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