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Merge pull request #674 from lioncash/sys-instrs 

dyncom: Implement RFE and SRS.
master
bunnei 2015-03-24 23:21:44 +07:00
parent eea0df8c52 a80d93685a
commit b3d4a10e29
1 changed files with 62 additions and 2 deletions
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64
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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@ -2156,7 +2156,22 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index)
return INTERPRETER_TRANSLATE(rev)(inst, index);
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("RFE"); }
static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
inst_base->cond = AL;
inst_base->idx = index;
inst_base->br = INDIRECT_BRANCH;
inst_base->load_r15 = 0;
inst_cream->inst = inst;
inst_cream->get_addr = get_calc_addr_op(inst);
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index)
{
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsb_inst));
@ -2570,7 +2585,23 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index)
inst_base->load_r15 = 1;
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); }
static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
inst_base->cond = AL;
inst_base->idx = index;
inst_base->br = NON_BRANCH;
inst_base->load_r15 = 0;
inst_cream->inst = inst;
inst_cream->get_addr = get_calc_addr_op(inst);
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst));
@ -5293,6 +5324,20 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
}
RFE_INST:
{
// RFE is unconditional
ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
u32 address = 0;
inst_cream->get_addr(cpu, inst_cream->inst, address, 1);
cpu->Cpsr = ReadMemory32(cpu, address);
cpu->Reg[15] = ReadMemory32(cpu, address + 4);
INC_PC(sizeof(ldst_inst));
goto DISPATCH;
}
RSB_INST:
{
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
@ -5934,6 +5979,21 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
}
SRS_INST:
{
// SRS is unconditional
ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
u32 address = 0;
inst_cream->get_addr(cpu, inst_cream->inst, address, 1);
WriteMemory32(cpu, address + 0, cpu->Reg[14]);
WriteMemory32(cpu, address + 4, cpu->Spsr_copy);
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC(sizeof(ldst_inst));
FETCH_INST;
GOTO_NEXT_INST;
}
SSAT_INST:
{