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@ -886,32 +886,92 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs)
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if (!state_tracker.TouchStencilProperties()) {
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if (!state_tracker.TouchStencilProperties()) {
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return;
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return;
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}
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}
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if (regs.stencil_two_side_enable) {
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bool update_references = state_tracker.TouchStencilReference();
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// Separate values per face
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bool update_write_mask = state_tracker.TouchStencilWriteMask();
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scheduler.Record(
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bool update_compare_masks = state_tracker.TouchStencilCompare();
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[front_ref = regs.stencil_front_ref, front_write_mask = regs.stencil_front_mask,
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if (state_tracker.TouchStencilSide(regs.stencil_two_side_enable != 0)) {
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front_test_mask = regs.stencil_front_func_mask, back_ref = regs.stencil_back_ref,
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update_references = true;
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back_write_mask = regs.stencil_back_mask,
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update_write_mask = true;
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back_test_mask = regs.stencil_back_func_mask](vk::CommandBuffer cmdbuf) {
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update_compare_masks = true;
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// Front face
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cmdbuf.SetStencilReference(VK_STENCIL_FACE_FRONT_BIT, front_ref);
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cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_FRONT_BIT, front_write_mask);
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cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_FRONT_BIT, front_test_mask);
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// Back face
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cmdbuf.SetStencilReference(VK_STENCIL_FACE_BACK_BIT, back_ref);
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cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_BACK_BIT, back_write_mask);
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cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_BACK_BIT, back_test_mask);
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});
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} else {
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// Front face defines both faces
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scheduler.Record([ref = regs.stencil_front_ref, write_mask = regs.stencil_front_mask,
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test_mask = regs.stencil_front_func_mask](vk::CommandBuffer cmdbuf) {
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cmdbuf.SetStencilReference(VK_STENCIL_FACE_FRONT_AND_BACK, ref);
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cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_FRONT_AND_BACK, write_mask);
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cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_FRONT_AND_BACK, test_mask);
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});
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}
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}
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if (update_references) {
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[&]() {
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if (regs.stencil_two_side_enable) {
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if (!state_tracker.CheckStencilReferenceFront(regs.stencil_front_ref) &&
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!state_tracker.CheckStencilReferenceBack(regs.stencil_back_ref)) {
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return;
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}
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} else {
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if (!state_tracker.CheckStencilReferenceFront(regs.stencil_front_ref)) {
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return;
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}
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}
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scheduler.Record([front_ref = regs.stencil_front_ref, back_ref = regs.stencil_back_ref,
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two_sided = regs.stencil_two_side_enable](vk::CommandBuffer cmdbuf) {
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const bool set_back = two_sided && front_ref != back_ref;
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// Front face
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cmdbuf.SetStencilReference(set_back ? VK_STENCIL_FACE_FRONT_BIT
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: VK_STENCIL_FACE_FRONT_AND_BACK,
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front_ref);
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if (set_back) {
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cmdbuf.SetStencilReference(VK_STENCIL_FACE_BACK_BIT, back_ref);
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}
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});
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}();
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}
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if (update_write_mask) {
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[&]() {
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if (regs.stencil_two_side_enable) {
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if (!state_tracker.CheckStencilWriteMaskFront(regs.stencil_front_mask) &&
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!state_tracker.CheckStencilWriteMaskBack(regs.stencil_back_mask)) {
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return;
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}
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} else {
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if (!state_tracker.CheckStencilWriteMaskFront(regs.stencil_front_mask)) {
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return;
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}
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}
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scheduler.Record([front_write_mask = regs.stencil_front_mask,
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back_write_mask = regs.stencil_back_mask,
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two_sided = regs.stencil_two_side_enable](vk::CommandBuffer cmdbuf) {
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const bool set_back = two_sided && front_write_mask != back_write_mask;
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// Front face
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cmdbuf.SetStencilWriteMask(set_back ? VK_STENCIL_FACE_FRONT_BIT
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: VK_STENCIL_FACE_FRONT_AND_BACK,
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front_write_mask);
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if (set_back) {
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cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_BACK_BIT, back_write_mask);
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}
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});
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}();
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}
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if (update_compare_masks) {
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[&]() {
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if (regs.stencil_two_side_enable) {
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if (!state_tracker.CheckStencilCompareMaskFront(regs.stencil_front_func_mask) &&
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!state_tracker.CheckStencilCompareMaskBack(regs.stencil_back_func_mask)) {
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return;
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}
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} else {
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if (!state_tracker.CheckStencilCompareMaskFront(regs.stencil_front_func_mask)) {
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return;
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}
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}
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scheduler.Record([front_test_mask = regs.stencil_front_func_mask,
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back_test_mask = regs.stencil_back_func_mask,
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two_sided = regs.stencil_two_side_enable](vk::CommandBuffer cmdbuf) {
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const bool set_back = two_sided && front_test_mask != back_test_mask;
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// Front face
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cmdbuf.SetStencilCompareMask(set_back ? VK_STENCIL_FACE_FRONT_BIT
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: VK_STENCIL_FACE_FRONT_AND_BACK,
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front_test_mask);
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if (set_back) {
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cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_BACK_BIT, back_test_mask);
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}
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});
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}();
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}
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state_tracker.ClearStencilReset();
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}
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}
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void RasterizerVulkan::UpdateLineWidth(Tegra::Engines::Maxwell3D::Regs& regs) {
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void RasterizerVulkan::UpdateLineWidth(Tegra::Engines::Maxwell3D::Regs& regs) {
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