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@ -38,14 +38,14 @@ void GlobalStorageOp(EmitContext& ctx, Register address, bool pointer_based, std
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continue;
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continue;
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}
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}
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const auto& ssbo{ctx.info.storage_buffers_descriptors[index]};
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const auto& ssbo{ctx.info.storage_buffers_descriptors[index]};
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ctx.Add("LDC.U64 DC.x,c{}[{}];" // ssbo_addr
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ctx.Add("LDC.U64 DC.x,c{}[{}];" // ssbo_addr
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"LDC.U32 RC.x,c{}[{}];" // ssbo_size_u32
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"LDC.U32 RC.x,c{}[{}];" // ssbo_size_u32
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"CVT.U64.U32 DC.y,RC.x;" // ssbo_size = ssbo_size_u32
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"CVT.U64.U32 DC.y,RC.x;" // ssbo_size = ssbo_size_u32
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"ADD.U64 DC.y,DC.y,DC.x;" // ssbo_end = ssbo_addr + ssbo_size
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"ADD.U64 DC.y,DC.y,DC.x;" // ssbo_end = ssbo_addr + ssbo_size
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"SGE.U64 RC.x,{}.x,DC.x;" // a = input_addr >= ssbo_addr ? -1 : 1
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"SGE.U64 RC.x,{}.x,DC.x;" // a = input_addr >= ssbo_addr ? -1 : 0
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"SLT.U64 RC.y,{}.x,DC.y;" // b = input_addr < ssbo_end ? -1 : 1
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"SLT.U64 RC.y,{}.x,DC.y;" // b = input_addr < ssbo_end ? -1 : 0
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"AND.U.CC RC.x,RC.x,RC.y;"
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"AND.U.CC RC.x,RC.x,RC.y;" // cond = a && b
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"IF NE.x;" // a && b
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"IF NE.x;" // if cond
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"SUB.U64 DC.x,{}.x,DC.x;", // offset = input_addr - ssbo_addr
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"SUB.U64 DC.x,{}.x,DC.x;", // offset = input_addr - ssbo_addr
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ssbo.cbuf_index, ssbo.cbuf_offset, ssbo.cbuf_index, ssbo.cbuf_offset + 8, address,
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ssbo.cbuf_index, ssbo.cbuf_offset, ssbo.cbuf_index, ssbo.cbuf_offset + 8, address,
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address, address);
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address, address);
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@ -65,7 +65,8 @@ void GlobalStorageOp(EmitContext& ctx, Register address, bool pointer_based, std
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if (!else_expr.empty()) {
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if (!else_expr.empty()) {
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ctx.Add("{}", else_expr);
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ctx.Add("{}", else_expr);
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}
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}
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for (size_t index = 0; index < num_buffers; ++index) {
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const size_t num_used_buffers{ctx.info.nvn_buffer_used.count()};
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for (size_t index = 0; index < num_used_buffers; ++index) {
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ctx.Add("ENDIF;");
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ctx.Add("ENDIF;");
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}
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}
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}
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}
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