arm: Adios armemu
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parent
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commit
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@ -1,114 +0,0 @@
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// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/arm/interpreter/arm_interpreter.h"
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#include "core/core.h"
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const static cpu_config_t arm11_cpu_info = {
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"armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE
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};
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ARM_Interpreter::ARM_Interpreter() {
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state = new ARMul_State;
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ARMul_EmulateInit();
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memset(state, 0, sizeof(ARMul_State));
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ARMul_NewState(state);
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state->abort_model = 0;
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state->cpu = (cpu_config_t*)&arm11_cpu_info;
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state->bigendSig = LOW;
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ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
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state->lateabtSig = LOW;
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// Reset the core to initial state
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ARMul_CoProInit(state);
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ARMul_Reset(state);
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state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
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state->Emulate = 3;
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state->pc = state->Reg[15] = 0x00000000;
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state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
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state->servaddr = 0xFFFF0000;
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}
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ARM_Interpreter::~ARM_Interpreter() {
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delete state;
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}
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void ARM_Interpreter::SetPC(u32 pc) {
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state->pc = state->Reg[15] = pc;
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}
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u32 ARM_Interpreter::GetPC() const {
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return state->pc;
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}
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u32 ARM_Interpreter::GetReg(int index) const {
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return state->Reg[index];
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}
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void ARM_Interpreter::SetReg(int index, u32 value) {
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state->Reg[index] = value;
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}
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u32 ARM_Interpreter::GetCPSR() const {
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return state->Cpsr;
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}
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void ARM_Interpreter::SetCPSR(u32 cpsr) {
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state->Cpsr = cpsr;
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}
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u64 ARM_Interpreter::GetTicks() const {
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return state->NumInstrs;
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}
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void ARM_Interpreter::AddTicks(u64 ticks) {
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state->NumInstrs += ticks;
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}
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void ARM_Interpreter::ExecuteInstructions(int num_instructions) {
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state->NumInstrsToExecute = num_instructions - 1;
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ARMul_Emulate32(state);
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}
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void ARM_Interpreter::SaveContext(Core::ThreadContext& ctx) {
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memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers));
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memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers));
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ctx.sp = state->Reg[13];
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ctx.lr = state->Reg[14];
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ctx.pc = state->pc;
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ctx.cpsr = state->Cpsr;
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ctx.fpscr = state->VFP[1];
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ctx.fpexc = state->VFP[2];
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ctx.reg_15 = state->Reg[15];
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ctx.mode = state->NextInstr;
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}
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void ARM_Interpreter::LoadContext(const Core::ThreadContext& ctx) {
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memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers));
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memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers));
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state->Reg[13] = ctx.sp;
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state->Reg[14] = ctx.lr;
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state->pc = ctx.pc;
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state->Cpsr = ctx.cpsr;
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state->VFP[1] = ctx.fpscr;
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state->VFP[2] = ctx.fpexc;
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state->Reg[15] = ctx.reg_15;
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state->NextInstr = ctx.mode;
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}
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void ARM_Interpreter::PrepareReschedule() {
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state->NumInstrsToExecute = 0;
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}
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@ -1,96 +0,0 @@
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// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include "common/common.h"
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#include "core/arm/arm_interface.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/armemu.h"
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class ARM_Interpreter final : virtual public ARM_Interface {
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public:
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ARM_Interpreter();
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~ARM_Interpreter();
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/**
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* Set the Program Counter to an address
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* @param pc Address to set PC to
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*/
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void SetPC(u32 pc) override;
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/*
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* Get the current Program Counter
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* @return Returns current PC
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*/
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u32 GetPC() const override;
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/**
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* Get an ARM register
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* @param index Register index (0-15)
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* @return Returns the value in the register
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*/
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u32 GetReg(int index) const override;
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/**
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* Set an ARM register
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* @param index Register index (0-15)
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* @param value Value to set register to
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*/
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void SetReg(int index, u32 value) override;
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/**
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* Get the current CPSR register
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* @return Returns the value of the CPSR register
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*/
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u32 GetCPSR() const override;
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/**
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* Set the current CPSR register
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* @param cpsr Value to set CPSR to
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*/
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void SetCPSR(u32 cpsr) override;
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/**
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* Returns the number of clock ticks since the last reset
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* @return Returns number of clock ticks
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*/
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u64 GetTicks() const override;
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/**
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* Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time)
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* @param ticks Number of ticks to advance the CPU core
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*/
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void AddTicks(u64 ticks) override;
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/**
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* Saves the current CPU context
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* @param ctx Thread context to save
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*/
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void SaveContext(Core::ThreadContext& ctx) override;
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/**
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* Loads a CPU context
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* @param ctx Thread context to load
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*/
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void LoadContext(const Core::ThreadContext& ctx) override;
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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void PrepareReschedule() override;
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protected:
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/**
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* Executes the given number of instructions
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* @param num_instructions Number of instructions to executes
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*/
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void ExecuteInstructions(int num_instructions) override;
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private:
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ARMul_State* state;
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};
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File diff suppressed because it is too large
Load Diff
@ -1,165 +0,0 @@
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/* armvirt.c -- ARMulator virtual memory interace: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* This file contains a complete ARMulator memory model, modelling a
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"virtual memory" system. A much simpler model can be found in armfast.c,
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and that model goes faster too, but has a fixed amount of memory. This
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model's memory has 64K pages, allocated on demand from a 64K entry page
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table. The routines PutWord and GetWord implement this. Pages are never
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freed as they might be needed again. A single area of memory may be
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defined to generate aborts. */
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/armemu.h"
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#include "core/mem_map.h"
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#define dumpstack 1
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#define dumpstacksize 0x10
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#define maxdmupaddr 0x0033a850
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/*ARMword ARMul_GetCPSR (ARMul_State * state) {
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return 0;
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}
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ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode) {
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return 0;
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}
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void ARMul_SetCPSR (ARMul_State * state, ARMword value) {
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}
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void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value) {
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}*/
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void ARMul_Icycles(ARMul_State * state, unsigned number, ARMword address) {
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}
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void ARMul_Ccycles(ARMul_State * state, unsigned number, ARMword address) {
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}
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ARMword ARMul_LoadInstrS(ARMul_State * state, ARMword address, ARMword isize) {
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state->NumScycles++;
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#ifdef HOURGLASS
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if ((state->NumScycles & HOURGLASS_RATE) == 0) {
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HOURGLASS;
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}
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#endif
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if (isize == 2)
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return (u16)Memory::Read16(address);
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else
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return (u32)Memory::Read32(address);
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}
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ARMword ARMul_LoadInstrN(ARMul_State * state, ARMword address, ARMword isize) {
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state->NumNcycles++;
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if (isize == 2)
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return (u16)Memory::Read16(address);
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else
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return (u32)Memory::Read32(address);
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}
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ARMword ARMul_ReLoadInstr(ARMul_State * state, ARMword address, ARMword isize) {
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ARMword data;
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if ((isize == 2) && (address & 0x2)) {
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ARMword lo;
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lo = (u16)Memory::Read16(address);
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return lo;
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}
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data = (u32)Memory::Read32(address);
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return data;
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}
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ARMword ARMul_ReadWord(ARMul_State * state, ARMword address) {
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ARMword data;
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data = Memory::Read32(address);
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return data;
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}
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ARMword ARMul_LoadWordS(ARMul_State * state, ARMword address) {
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state->NumScycles++;
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return ARMul_ReadWord(state, address);
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}
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ARMword ARMul_LoadWordN(ARMul_State * state, ARMword address) {
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state->NumNcycles++;
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return ARMul_ReadWord(state, address);
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}
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ARMword ARMul_LoadHalfWord(ARMul_State * state, ARMword address) {
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state->NumNcycles++;
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return (u16)Memory::Read16(address);;
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}
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ARMword ARMul_ReadByte(ARMul_State * state, ARMword address) {
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return (u8)Memory::Read8(address);
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}
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ARMword ARMul_LoadByte(ARMul_State * state, ARMword address) {
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state->NumNcycles++;
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return ARMul_ReadByte(state, address);
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}
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void ARMul_StoreHalfWord(ARMul_State * state, ARMword address, ARMword data) {
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state->NumNcycles++;
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Memory::Write16(address, data);
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}
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void ARMul_StoreByte(ARMul_State * state, ARMword address, ARMword data) {
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state->NumNcycles++;
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ARMul_WriteByte(state, address, data);
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}
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ARMword ARMul_SwapWord(ARMul_State * state, ARMword address, ARMword data) {
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ARMword temp;
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state->NumNcycles++;
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temp = ARMul_ReadWord(state, address);
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state->NumNcycles++;
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Memory::Write32(address, data);
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return temp;
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}
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ARMword ARMul_SwapByte(ARMul_State * state, ARMword address, ARMword data) {
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ARMword temp;
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temp = ARMul_LoadByte(state, address);
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Memory::Write8(address, data);
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return temp;
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}
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void ARMul_WriteWord(ARMul_State * state, ARMword address, ARMword data) {
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Memory::Write32(address, data);
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}
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void ARMul_WriteByte(ARMul_State * state, ARMword address, ARMword data)
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{
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Memory::Write8(address, data);
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}
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void ARMul_StoreWordS(ARMul_State * state, ARMword address, ARMword data)
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{
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state->NumScycles++;
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ARMul_WriteWord(state, address, data);
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}
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void ARMul_StoreWordN(ARMul_State * state, ARMword address, ARMword data)
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{
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state->NumNcycles++;
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ARMul_WriteWord(state, address, data);
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}
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@ -1,513 +0,0 @@
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/* thumbemu.c -- Thumb instruction emulation.
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Copyright (C) 1996, Cygnus Software Technologies Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* We can provide simple Thumb simulation by decoding the Thumb
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instruction into its corresponding ARM instruction, and using the
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existing ARM simulator. */
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#include "core/arm/skyeye_common/skyeye_defs.h"
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#ifndef MODET /* required for the Thumb instruction support */
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#if 1
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#error "MODET needs to be defined for the Thumb world to work"
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#else
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#define MODET (1)
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#endif
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#endif
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/armemu.h"
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#include "core/arm/skyeye_common/armos.h"
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/* Decode a 16bit Thumb instruction. The instruction is in the low
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16-bits of the tinstr field, with the following Thumb instruction
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held in the high 16-bits. Passing in two Thumb instructions allows
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easier simulation of the special dual BL instruction. */
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tdstate
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ARMul_ThumbDecode (
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ARMul_State *state,
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ARMword pc,
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ARMword tinstr,
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ARMword *ainstr)
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{
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tdstate valid = t_decoded; /* default assumes a valid instruction */
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ARMword next_instr;
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if (state->bigendSig) {
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next_instr = tinstr & 0xFFFF;
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tinstr >>= 16;
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}
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else {
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next_instr = tinstr >> 16;
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tinstr &= 0xFFFF;
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}
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#if 1 /* debugging to catch non updates */
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*ainstr = 0xDEADC0DE;
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#endif
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switch ((tinstr & 0xF800) >> 11) {
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case 0: /* LSL */
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case 1: /* LSR */
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case 2: /* ASR */
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/* Format 1 */
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*ainstr = 0xE1B00000 /* base opcode */
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| ((tinstr & 0x1800) >> (11 - 5)) /* shift type */
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|((tinstr & 0x07C0) << (7 - 6)) /* imm5 */
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|((tinstr & 0x0038) >> 3) /* Rs */
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|((tinstr & 0x0007) << 12); /* Rd */
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break;
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case 3: /* ADD/SUB */
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/* Format 2 */
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{
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ARMword subset[4] = {
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0xE0900000, /* ADDS Rd,Rs,Rn */
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0xE0500000, /* SUBS Rd,Rs,Rn */
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0xE2900000, /* ADDS Rd,Rs,#imm3 */
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0xE2500000 /* SUBS Rd,Rs,#imm3 */
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};
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/* It is quicker indexing into a table, than performing switch
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or conditionals: */
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*ainstr = subset[(tinstr & 0x0600) >> 9] /* base opcode */
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|((tinstr & 0x01C0) >> 6) /* Rn or imm3 */
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|((tinstr & 0x0038) << (16 - 3)) /* Rs */
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|((tinstr & 0x0007) << (12 - 0)); /* Rd */
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}
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break;
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case 4: /* MOV */
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case 5: /* CMP */
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case 6: /* ADD */
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case 7: /* SUB */
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/* Format 3 */
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{
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ARMword subset[4] = {
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0xE3B00000, /* MOVS Rd,#imm8 */
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0xE3500000, /* CMP Rd,#imm8 */
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0xE2900000, /* ADDS Rd,Rd,#imm8 */
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0xE2500000, /* SUBS Rd,Rd,#imm8 */
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};
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*ainstr = subset[(tinstr & 0x1800) >> 11] /* base opcode */
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|((tinstr & 0x00FF) >> 0) /* imm8 */
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|((tinstr & 0x0700) << (16 - 8)) /* Rn */
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|((tinstr & 0x0700) << (12 - 8)); /* Rd */
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}
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break;
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case 8: /* Arithmetic and high register transfers */
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/* TODO: Since the subsets for both Format 4 and Format 5
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instructions are made up of different ARM encodings, we could
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save the following conditional, and just have one large
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subset. */
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if ((tinstr & (1 << 10)) == 0) {
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/* Format 4 */
|
||||
enum OpcodeType { t_norm, t_shift, t_neg, t_mul };
|
||||
struct ThumbOpcode {
|
||||
ARMword opcode;
|
||||
OpcodeType otype;
|
||||
};
|
||||
|
||||
ThumbOpcode subset[16] = {
|
||||
{
|
||||
0xE0100000, t_norm}, /* ANDS Rd,Rd,Rs */
|
||||
{
|
||||
0xE0300000, t_norm}, /* EORS Rd,Rd,Rs */
|
||||
{
|
||||
0xE1B00010, t_shift}, /* MOVS Rd,Rd,LSL Rs */
|
||||
{
|
||||
0xE1B00030, t_shift}, /* MOVS Rd,Rd,LSR Rs */
|
||||
{
|
||||
0xE1B00050, t_shift}, /* MOVS Rd,Rd,ASR Rs */
|
||||
{
|
||||
0xE0B00000, t_norm}, /* ADCS Rd,Rd,Rs */
|
||||
{
|
||||
0xE0D00000, t_norm}, /* SBCS Rd,Rd,Rs */
|
||||
{
|
||||
0xE1B00070, t_shift}, /* MOVS Rd,Rd,ROR Rs */
|
||||
{
|
||||
0xE1100000, t_norm}, /* TST Rd,Rs */
|
||||
{
|
||||
0xE2700000, t_neg}, /* RSBS Rd,Rs,#0 */
|
||||
{
|
||||
0xE1500000, t_norm}, /* CMP Rd,Rs */
|
||||
{
|
||||
0xE1700000, t_norm}, /* CMN Rd,Rs */
|
||||
{
|
||||
0xE1900000, t_norm}, /* ORRS Rd,Rd,Rs */
|
||||
{
|
||||
0xE0100090, t_mul}, /* MULS Rd,Rd,Rs */
|
||||
{
|
||||
0xE1D00000, t_norm}, /* BICS Rd,Rd,Rs */
|
||||
{
|
||||
0xE1F00000, t_norm} /* MVNS Rd,Rs */
|
||||
};
|
||||
*ainstr = subset[(tinstr & 0x03C0) >> 6].opcode; /* base */
|
||||
switch (subset[(tinstr & 0x03C0) >> 6].otype) {
|
||||
case t_norm:
|
||||
*ainstr |= ((tinstr & 0x0007) << 16) /* Rn */
|
||||
|((tinstr & 0x0007) << 12) /* Rd */
|
||||
|((tinstr & 0x0038) >> 3); /* Rs */
|
||||
break;
|
||||
case t_shift:
|
||||
*ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
|
||||
|((tinstr & 0x0007) >> 0) /* Rm */
|
||||
|((tinstr & 0x0038) << (8 - 3)); /* Rs */
|
||||
break;
|
||||
case t_neg:
|
||||
*ainstr |= ((tinstr & 0x0007) << 12) /* Rd */
|
||||
|((tinstr & 0x0038) << (16 - 3)); /* Rn */
|
||||
break;
|
||||
case t_mul:
|
||||
*ainstr |= ((tinstr & 0x0007) << 16) /* Rd */
|
||||
|((tinstr & 0x0007) << 8) /* Rs */
|
||||
|((tinstr & 0x0038) >> 3); /* Rm */
|
||||
break;
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* Format 5 */
|
||||
ARMword Rd = ((tinstr & 0x0007) >> 0);
|
||||
ARMword Rs = ((tinstr & 0x0038) >> 3);
|
||||
if (tinstr & (1 << 7))
|
||||
Rd += 8;
|
||||
if (tinstr & (1 << 6))
|
||||
Rs += 8;
|
||||
switch ((tinstr & 0x03C0) >> 6) {
|
||||
case 0x1: /* ADD Rd,Rd,Hs */
|
||||
case 0x2: /* ADD Hd,Hd,Rs */
|
||||
case 0x3: /* ADD Hd,Hd,Hs */
|
||||
*ainstr = 0xE0800000 /* base */
|
||||
| (Rd << 16) /* Rn */
|
||||
|(Rd << 12) /* Rd */
|
||||
|(Rs << 0); /* Rm */
|
||||
break;
|
||||
case 0x5: /* CMP Rd,Hs */
|
||||
case 0x6: /* CMP Hd,Rs */
|
||||
case 0x7: /* CMP Hd,Hs */
|
||||
*ainstr = 0xE1500000 /* base */
|
||||
| (Rd << 16) /* Rn */
|
||||
|(Rd << 12) /* Rd */
|
||||
|(Rs << 0); /* Rm */
|
||||
break;
|
||||
case 0x9: /* MOV Rd,Hs */
|
||||
case 0xA: /* MOV Hd,Rs */
|
||||
case 0xB: /* MOV Hd,Hs */
|
||||
*ainstr = 0xE1A00000 /* base */
|
||||
| (Rd << 16) /* Rn */
|
||||
|(Rd << 12) /* Rd */
|
||||
|(Rs << 0); /* Rm */
|
||||
break;
|
||||
case 0xC: /* BX Rs */
|
||||
case 0xD: /* BX Hs */
|
||||
*ainstr = 0xE12FFF10 /* base */
|
||||
| ((tinstr & 0x0078) >> 3); /* Rd */
|
||||
break;
|
||||
case 0x0: /* UNDEFINED */
|
||||
case 0x4: /* UNDEFINED */
|
||||
case 0x8: /* UNDEFINED */
|
||||
valid = t_undefined;
|
||||
break;
|
||||
case 0xE: /* BLX */
|
||||
case 0xF: /* BLX */
|
||||
if (state->is_v5) {
|
||||
*ainstr = 0xE1200030 /* base */
|
||||
|(Rs << 0); /* Rm */
|
||||
} else {
|
||||
valid = t_undefined;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 9: /* LDR Rd,[PC,#imm8] */
|
||||
/* Format 6 */
|
||||
*ainstr = 0xE59F0000 /* base */
|
||||
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
||||
|((tinstr & 0x00FF) << (2 - 0)); /* off8 */
|
||||
break;
|
||||
case 10:
|
||||
case 11:
|
||||
/* TODO: Format 7 and Format 8 perform the same ARM encoding, so
|
||||
the following could be merged into a single subset, saving on
|
||||
the following boolean: */
|
||||
if ((tinstr & (1 << 9)) == 0) {
|
||||
/* Format 7 */
|
||||
ARMword subset[4] = {
|
||||
0xE7800000, /* STR Rd,[Rb,Ro] */
|
||||
0xE7C00000, /* STRB Rd,[Rb,Ro] */
|
||||
0xE7900000, /* LDR Rd,[Rb,Ro] */
|
||||
0xE7D00000 /* LDRB Rd,[Rb,Ro] */
|
||||
};
|
||||
*ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
|
||||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
||||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
||||
|((tinstr & 0x01C0) >> 6); /* Ro */
|
||||
}
|
||||
else {
|
||||
/* Format 8 */
|
||||
ARMword subset[4] = {
|
||||
0xE18000B0, /* STRH Rd,[Rb,Ro] */
|
||||
0xE19000D0, /* LDRSB Rd,[Rb,Ro] */
|
||||
0xE19000B0, /* LDRH Rd,[Rb,Ro] */
|
||||
0xE19000F0 /* LDRSH Rd,[Rb,Ro] */
|
||||
};
|
||||
*ainstr = subset[(tinstr & 0x0C00) >> 10] /* base */
|
||||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
||||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
||||
|((tinstr & 0x01C0) >> 6); /* Ro */
|
||||
}
|
||||
break;
|
||||
case 12: /* STR Rd,[Rb,#imm5] */
|
||||
case 13: /* LDR Rd,[Rb,#imm5] */
|
||||
case 14: /* STRB Rd,[Rb,#imm5] */
|
||||
case 15: /* LDRB Rd,[Rb,#imm5] */
|
||||
/* Format 9 */
|
||||
{
|
||||
ARMword subset[4] = {
|
||||
0xE5800000, /* STR Rd,[Rb,#imm5] */
|
||||
0xE5900000, /* LDR Rd,[Rb,#imm5] */
|
||||
0xE5C00000, /* STRB Rd,[Rb,#imm5] */
|
||||
0xE5D00000 /* LDRB Rd,[Rb,#imm5] */
|
||||
};
|
||||
/* The offset range defends on whether we are transferring a
|
||||
byte or word value: */
|
||||
*ainstr = subset[(tinstr & 0x1800) >> 11] /* base */
|
||||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
||||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
||||
|((tinstr & 0x07C0) >> (6 - ((tinstr & (1 << 12)) ? 0 : 2))); /* off5 */
|
||||
}
|
||||
break;
|
||||
case 16: /* STRH Rd,[Rb,#imm5] */
|
||||
case 17: /* LDRH Rd,[Rb,#imm5] */
|
||||
/* Format 10 */
|
||||
*ainstr = ((tinstr & (1 << 11)) /* base */
|
||||
? 0xE1D000B0 /* LDRH */
|
||||
: 0xE1C000B0) /* STRH */
|
||||
|((tinstr & 0x0007) << (12 - 0)) /* Rd */
|
||||
|((tinstr & 0x0038) << (16 - 3)) /* Rb */
|
||||
|((tinstr & 0x01C0) >> (6 - 1)) /* off5, low nibble */
|
||||
|((tinstr & 0x0600) >> (9 - 8)); /* off5, high nibble */
|
||||
break;
|
||||
case 18: /* STR Rd,[SP,#imm8] */
|
||||
case 19: /* LDR Rd,[SP,#imm8] */
|
||||
/* Format 11 */
|
||||
*ainstr = ((tinstr & (1 << 11)) /* base */
|
||||
? 0xE59D0000 /* LDR */
|
||||
: 0xE58D0000) /* STR */
|
||||
|((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
||||
|((tinstr & 0x00FF) << 2); /* off8 */
|
||||
break;
|
||||
case 20: /* ADD Rd,PC,#imm8 */
|
||||
case 21: /* ADD Rd,SP,#imm8 */
|
||||
/* Format 12 */
|
||||
if ((tinstr & (1 << 11)) == 0) {
|
||||
/* NOTE: The PC value used here should by word aligned */
|
||||
/* We encode shift-left-by-2 in the rotate immediate field,
|
||||
so no shift of off8 is needed. */
|
||||
*ainstr = 0xE28F0F00 /* base */
|
||||
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
||||
|(tinstr & 0x00FF); /* off8 */
|
||||
}
|
||||
else {
|
||||
/* We encode shift-left-by-2 in the rotate immediate field,
|
||||
so no shift of off8 is needed. */
|
||||
*ainstr = 0xE28D0F00 /* base */
|
||||
| ((tinstr & 0x0700) << (12 - 8)) /* Rd */
|
||||
|(tinstr & 0x00FF); /* off8 */
|
||||
}
|
||||
break;
|
||||
case 22:
|
||||
case 23:
|
||||
if ((tinstr & 0x0F00) == 0x0000) {
|
||||
/* Format 13 */
|
||||
/* NOTE: The instruction contains a shift left of 2
|
||||
equivalent (implemented as ROR #30): */
|
||||
*ainstr = ((tinstr & (1 << 7)) /* base */
|
||||
? 0xE24DDF00 /* SUB */
|
||||
: 0xE28DDF00) /* ADD */
|
||||
|(tinstr & 0x007F); /* off7 */
|
||||
}
|
||||
else if ((tinstr & 0x0F00) == 0x0e00)
|
||||
*ainstr = 0xEF000000 | SWI_Breakpoint;
|
||||
else {
|
||||
/* Format 14 */
|
||||
ARMword subset[4] = {
|
||||
0xE92D0000, /* STMDB sp!,{rlist} */
|
||||
0xE92D4000, /* STMDB sp!,{rlist,lr} */
|
||||
0xE8BD0000, /* LDMIA sp!,{rlist} */
|
||||
0xE8BD8000 /* LDMIA sp!,{rlist,pc} */
|
||||
};
|
||||
*ainstr = subset[((tinstr & (1 << 11)) >> 10) | ((tinstr & (1 << 8)) >> 8)] /* base */
|
||||
|(tinstr & 0x00FF); /* mask8 */
|
||||
}
|
||||
break;
|
||||
case 24: /* STMIA */
|
||||
case 25: /* LDMIA */
|
||||
/* Format 15 */
|
||||
*ainstr = ((tinstr & (1 << 11)) /* base */
|
||||
? 0xE8B00000 /* LDMIA */
|
||||
: 0xE8A00000) /* STMIA */
|
||||
|((tinstr & 0x0700) << (16 - 8)) /* Rb */
|
||||
|(tinstr & 0x00FF); /* mask8 */
|
||||
break;
|
||||
case 26: /* Bcc */
|
||||
case 27: /* Bcc/SWI */
|
||||
if ((tinstr & 0x0F00) == 0x0F00) {
|
||||
if (tinstr == (ARMul_ABORTWORD & 0xffff) &&
|
||||
state->AbortAddr == pc) {
|
||||
*ainstr = ARMul_ABORTWORD;
|
||||
break;
|
||||
}
|
||||
/* Format 17 : SWI */
|
||||
*ainstr = 0xEF000000;
|
||||
/* Breakpoint must be handled specially. */
|
||||
if ((tinstr & 0x00FF) == 0x18)
|
||||
*ainstr |= ((tinstr & 0x00FF) << 16);
|
||||
/* New breakpoint value. See gdb/arm-tdep.c */
|
||||
else if ((tinstr & 0x00FF) == 0xFE)
|
||||
*ainstr |= SWI_Breakpoint;
|
||||
else
|
||||
*ainstr |= (tinstr & 0x00FF);
|
||||
}
|
||||
else if ((tinstr & 0x0F00) != 0x0E00) {
|
||||
/* Format 16 */
|
||||
int doit = FALSE;
|
||||
/* TODO: Since we are doing a switch here, we could just add
|
||||
the SWI and undefined instruction checks into this
|
||||
switch to same on a couple of conditionals: */
|
||||
switch ((tinstr & 0x0F00) >> 8) {
|
||||
case EQ:
|
||||
doit = ZFLAG;
|
||||
break;
|
||||
case NE:
|
||||
doit = !ZFLAG;
|
||||
break;
|
||||
case VS:
|
||||
doit = VFLAG;
|
||||
break;
|
||||
case VC:
|
||||
doit = !VFLAG;
|
||||
break;
|
||||
case MI:
|
||||
doit = NFLAG;
|
||||
break;
|
||||
case PL:
|
||||
doit = !NFLAG;
|
||||
break;
|
||||
case CS:
|
||||
doit = CFLAG;
|
||||
break;
|
||||
case CC:
|
||||
doit = !CFLAG;
|
||||
break;
|
||||
case HI:
|
||||
doit = (CFLAG && !ZFLAG);
|
||||
break;
|
||||
case LS:
|
||||
doit = (!CFLAG || ZFLAG);
|
||||
break;
|
||||
case GE:
|
||||
doit = ((!NFLAG && !VFLAG)
|
||||
|| (NFLAG && VFLAG));
|
||||
break;
|
||||
case LT:
|
||||
doit = ((NFLAG && !VFLAG)
|
||||
|| (!NFLAG && VFLAG));
|
||||
break;
|
||||
case GT:
|
||||
doit = ((!NFLAG && !VFLAG && !ZFLAG)
|
||||
|| (NFLAG && VFLAG && !ZFLAG));
|
||||
break;
|
||||
case LE:
|
||||
doit = ((NFLAG && !VFLAG)
|
||||
|| (!NFLAG && VFLAG)) || ZFLAG;
|
||||
break;
|
||||
}
|
||||
if (doit) {
|
||||
state->Reg[15] = (pc + 4
|
||||
+ (((tinstr & 0x7F) << 1)
|
||||
| ((tinstr & (1 << 7)) ?
|
||||
0xFFFFFF00 : 0)));
|
||||
FLUSHPIPE;
|
||||
}
|
||||
valid = t_branch;
|
||||
}
|
||||
else /* UNDEFINED : cc=1110(AL) uses different format */
|
||||
valid = t_undefined;
|
||||
break;
|
||||
case 28: /* B */
|
||||
/* Format 18 */
|
||||
state->Reg[15] = (pc + 4 + (((tinstr & 0x3FF) << 1)
|
||||
| ((tinstr & (1 << 10)) ?
|
||||
0xFFFFF800 : 0)));
|
||||
FLUSHPIPE;
|
||||
valid = t_branch;
|
||||
break;
|
||||
case 29:
|
||||
if(tinstr & 0x1)
|
||||
valid = t_undefined;
|
||||
else{
|
||||
/* BLX 1 for armv5t and above */
|
||||
ARMword tmp = (pc + 2);
|
||||
state->Reg[15] =
|
||||
(state->Reg[14] + ((tinstr & 0x07FF) << 1)) & 0xFFFFFFFC;
|
||||
state->Reg[14] = (tmp | 1);
|
||||
CLEART;
|
||||
LOG_DEBUG(Core_ARM11, "After BLX(1),LR=0x%x,PC=0x%x, offset=0x%x", state->Reg[14], state->Reg[15], (tinstr &0x7FF) << 1);
|
||||
valid = t_branch;
|
||||
FLUSHPIPE;
|
||||
}
|
||||
break;
|
||||
case 30: /* BL instruction 1 */
|
||||
/* Format 19 */
|
||||
/* There is no single ARM instruction equivalent for this Thumb
|
||||
instruction. To keep the simulation simple (from the user
|
||||
perspective) we check if the following instruction is the
|
||||
second half of this BL, and if it is we simulate it
|
||||
immediately. */
|
||||
state->Reg[14] = state->Reg[15]
|
||||
+ (((tinstr & 0x07FF) << 12)
|
||||
| ((tinstr & (1 << 10)) ? 0xFF800000 : 0));
|
||||
valid = t_branch; /* in-case we don't have the 2nd half */
|
||||
//tinstr = next_instr; /* move the instruction down */
|
||||
//if (((tinstr & 0xF800) >> 11) != 31)
|
||||
// break; /* exit, since not correct instruction */
|
||||
/* else we fall through to process the second half of the BL */
|
||||
//pc += 2; /* point the pc at the 2nd half */
|
||||
state->Reg[15] = pc + 2;
|
||||
FLUSHPIPE;
|
||||
break;
|
||||
case 31: /* BL instruction 2 */
|
||||
/* Format 19 */
|
||||
/* There is no single ARM instruction equivalent for this
|
||||
instruction. Also, it should only ever be matched with the
|
||||
fmt19 "BL instruction 1" instruction. However, we do allow
|
||||
the simulation of it on its own, with undefined results if
|
||||
r14 is not suitably initialised. */
|
||||
{
|
||||
ARMword tmp = (pc + 2);
|
||||
state->Reg[15] =
|
||||
(state->Reg[14] + ((tinstr & 0x07FF) << 1));
|
||||
state->Reg[14] = (tmp | 1);
|
||||
valid = t_branch;
|
||||
FLUSHPIPE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return valid;
|
||||
}
|
||||
Loading…
Reference in New Issue