CCF_100
/
yuzu-mirror
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

dyncom: Handle modifying the APSR via an MRC instruction

master
Lioncash 2015-12-28 07:52:04 +07:00
parent 8f39297c53
commit fddfe946c8
1 changed files with 9 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
Unescape Escape View File

@ -4696,18 +4696,15 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
mrc_inst* inst_cream = (mrc_inst*)inst_base->component; mrc_inst* inst_cream = (mrc_inst*)inst_base->component;
unsigned int inst = inst_cream->inst; if (inst_cream->cp_num == 15) {
if (inst_cream->Rd == 15) { const uint32_t value = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2);
DEBUG_MSG;
} if (inst_cream->Rd == 15) {
if (inst_cream->inst == 0xeef04a10) { cpu->Cpsr = (cpu->Cpsr & ~0xF0000000) | (value & 0xF0000000);
// Undefined instruction fmrx LOAD_NZCVT;
RD = 0x20000000; } else {
CITRA_IGNORE_EXIT(-1); RD = value;
goto END; }
} else {
if (inst_cream->cp_num == 15)
RD = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2);
} }
} }
cpu->Reg[15] += cpu->GetInstructionSize(); cpu->Reg[15] += cpu->GetInstructionSize();