gl_shader_decompiler: Implement TEXS component mask.

master
bunnei 2018-06-03 12:08:17 +07:00
parent bb9d39b8fe
commit 1efcba346a
2 changed files with 26 additions and 9 deletions

@ -270,8 +270,22 @@ union Instruction {
} tex; } tex;
union { union {
// TODO(bunnei): This is just a guess, needs to be verified BitField<50, 3, u64> component_mask_selector;
BitField<52, 1, u64> enable_g_component; BitField<28, 8, Register> gpr28;
bool HasTwoDestinations() const {
return gpr28.Value() != Register::ZeroIndex;
}
bool IsComponentEnabled(size_t component) const {
static constexpr std::array<size_t, 5> one_dest_mask{0x1, 0x2, 0x4, 0x8, 0x3};
static constexpr std::array<size_t, 5> two_dest_mask{0x7, 0xb, 0xd, 0xe, 0xf};
const auto& mask{HasTwoDestinations() ? two_dest_mask : one_dest_mask};
ASSERT(component_mask_selector < mask.size());
return ((1 << component) & mask[component_mask_selector]) != 0;
}
} texs; } texs;
BitField<61, 1, u64> is_b_imm; BitField<61, 1, u64> is_b_imm;

@ -938,18 +938,21 @@ private:
// TEXS has two destination registers. RG goes into gpr0+0 and gpr0+1, and BA goes // TEXS has two destination registers. RG goes into gpr0+0 and gpr0+1, and BA goes
// into gpr28+0 and gpr28+1 // into gpr28+0 and gpr28+1
size_t offset{}; size_t offset{};
for (const auto& dest : {instr.gpr0.Value(), instr.gpr28.Value()}) { for (const auto& dest : {instr.gpr0.Value(), instr.gpr28.Value()}) {
for (unsigned elem = 0; elem < 2; ++elem) { for (unsigned elem = 0; elem < 2; ++elem) {
if (dest + elem >= Register::ZeroIndex) { if (!instr.texs.IsComponentEnabled(elem)) {
// Skip invalid register values // Skip disabled components
break; continue;
} }
regs.SetRegisterToFloat(dest, elem + offset, texture, 1, 4, false, elem); regs.SetRegisterToFloat(dest, elem + offset, texture, 1, 4, false, elem);
if (!instr.texs.enable_g_component) {
// Skip the second component
break;
}
} }
if (!instr.texs.HasTwoDestinations()) {
// Skip the second destination
break;
}
offset += 2; offset += 2;
} }
--shader.scope; --shader.scope;